Thread (54 messages) 54 messages, 4 authors, 2021-05-28

Re: [PATCH 11/16] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver

From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: 2021-05-21 15:04:42
Also in: linux-arm-kernel, linux-clk, linux-renesas-soc, linux-serial, lkml

Hi Prabhakar,

On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar
[off-list ref] wrote:
Document the device tree bindings of the Renesas RZ/G2L SoC clock
driver in Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Thanks for your patch!
quoted hunk ↗ jump to hunk
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas RZ/G2L Clock Pulse Generator / Module Stop and Software Reset
(Module Standby Mode
+
+maintainers:
+  - Geert Uytterhoeven [off-list ref]
+
+description: |
+  On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and MSTP
+  (Module Stop and Software Reset) share the same register block.
+
+  They provide the following functionalities:
+    - The CPG block generates various core clocks,
+    - The MSTP block provides two functions:
+        1. Module Stop, providing a Clock Domain to control the clock supply
+           to individual SoC devices,
+        2. Reset Control, to perform a software reset of individual SoC devices.
+
+properties:
+  compatible:
+    const: renesas,r9a07g044l-cpg  # RZ/G2L
renesas,r9a07g044-cpg?

I believe it's the same block on RZ/G2L ('044l) and RZ/G2LC ('044c).
+  '#clock-cells':
+    description: |
+      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
+        and a core clock reference, as defined in
+        <dt-bindings/clock/*-cpg-mssr.h>
<dt-bindings/clock/r9a07g044l-cpg.h>
+      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
+        a module number, as defined in the datasheet.
Also in <dt-bindings/clock/r9a07g044l-cpg.h>?
+    const: 2
+
+  '#power-domain-cells':
+    description:
+      SoC devices that are part of the CPG/MSTP Clock Domain and can be
+      power-managed through Module Stop should refer to the CPG device node
+      in their "power-domains" property, as documented by the generic PM Domain
+      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
+    const: 0
+
+  '#reset-cells':
+    description:
+      The single reset specifier cell must be the module number, as defined in
+      the datasheet.
Also in <dt-bindings/clock/r9a07g044l-cpg.h>?
+    const: 1
Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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