Re: [PATCH net-next v3 v3 1/2] dt-bindings: net: xilinx_axienet: Document additional clocks

On Wed, Mar 24, 2021 at 11:19 AM Robert Hancock
[off-list ref] wrote:

On Wed, 2021-03-24 at 11:08 -0600, Rob Herring wrote:

quoted

On Fri, Mar 12, 2021 at 01:52:13PM -0600, Robert Hancock wrote:

quoted

Update DT bindings to describe all of the clocks that the axienet
driver will now be able to make use of.

Signed-off-by: Robert Hancock <redacted>
---
 .../bindings/net/xilinx_axienet.txt           | 25 ++++++++++++++-----
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt

b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
index 2cd452419ed0..b8e4894bc634 100644

--- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt
+++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt

@@ -42,11 +42,23 @@ Optional properties:
              support both 1000BaseX and SGMII modes. If set, the phy-mode
              should be set to match the mode selected on core reset (i.e.
              by the basex_or_sgmii core input line).
-- clocks   : AXI bus clock for the device. Refer to common clock bindings.
-             Used to calculate MDIO clock divisor. If not specified, it is
-             auto-detected from the CPU clock (but only on platforms where
-             this is possible). New device trees should specify this - the
-             auto detection is only for backward compatibility.
+- clock-names:       Tuple listing input clock names. Possible clocks:
+             s_axi_lite_clk: Clock for AXI register slave interface
+             axis_clk: AXI4-Stream clock for TXD RXD TXC and RXS

interfaces
+             ref_clk: Ethernet reference clock, used by signal delay
+                      primitives and transceivers
+             mgt_clk: MGT reference clock (used by optional internal
+                      PCS/PMA PHY)

'_clk' is redundant.

True, but there are existing device trees which already referenced these names
because those are what was used by the Xilinx version of this driver and hence
the Xilinx device tree generation software. So for compatibility I think we are
kind of stuck with those names..

upstream? If not, then it doesn't matter what downstream is doing.
However, this isn't that important, so it's fine.

Acked-by: Rob Herring <robh@kernel.org>