Re: [PATCH 1/2] arm64: dts: ti: k3-am64: Add SERDES DT node
From: Kishon Vijay Abraham I <hidden>
Date: 2021-03-19 14:31:03
Also in:
linux-arm-kernel, lkml
Hi Aswath, On 19/03/21 1:30 pm, Aswath Govindraju wrote:
quoted hunk ↗ jump to hunk
From: Kishon Vijay Abraham I <redacted> Add SERDES DT node for the single one lane SERDES present in AM64. Signed-off-by: Kishon Vijay Abraham I <redacted> Signed-off-by: Aswath Govindraju <redacted> --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 52 ++++++++++++++++++++++++ 1 file changed, 52 insertions(+)diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index a03b66456062..5a62a96c048c 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi@@ -5,6 +5,17 @@ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <dt-bindings/phy/phy-cadence-torrent.h>
One of my patches in other series which renames the header file will cause issues here :-/ http://lore.kernel.org/r/20210319124128.13308-9-kishon@ti.com (local) We'll need a immutable tag for this as well.
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: serdes-refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };Clock frequency of serdes_refclk depends on how it is tied in the EVM. In the case of AM64EVM there is no external clock generator. It should be something like in https://github.com/kishon/linux-wip/commit/e5196b0819d334ce8a21b398b7c47557a145d250 Thanks Kishon
quoted hunk ↗ jump to hunk
+}; + &cbass_main { oc_sram: sram@70000000 { compatible = "mmio-sram";@@ -184,6 +195,12 @@ reg = <0x4044 0x8>; #phy-cells = <1>; }; + + serdes_ln_ctrl: mux { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ + }; }; main_uart0: serial@2800000 {@@ -477,6 +494,41 @@ }; }; + serdes_wiz0: wiz@f000000 { + compatible = "ti,am64-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; + assigned-clocks = <&k3_clks 162 1>; + assigned-clock-parents = <&k3_clks 162 5>; + + serdes0: serdes@f000000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f000000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 162 1>, + <&k3_clks 162 1>, + <&k3_clks 162 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + }; + }; + cpts@39000000 { compatible = "ti,j721e-cpts"; reg = <0x0 0x39000000 0x0 0x400>;