On Tue, Mar 16, 2021 at 11:15:47AM +0530, Manivannan Sadhasivam wrote:

On Mon, Mar 08, 2021 at 07:18:29PM +0200, Cristian Ciocaltea wrote:

quoted

There are a few issues with the setup of the Actions Semi Owl S500 SoC's
clock chain involving AHPPREDIV, H and AHB clocks:

* AHBPREDIV clock is defined as a muxer only, although it also acts as
  a divider.
* H clock is defined as a standard divider, although the raw value zero
  is not supported.

What do you mean by not supported? The datasheet lists "0" as the valid divisor
value for divide by 1.

Unfortunately CMU_BUSCLK1 is not documented in my S500 Datasheet
(Version: 1.6, 2016-03-07). Do you have a newer (or a more official)
one?

The reference xapp-le code snipped is:

static struct owl_div divider_H_CLK = {
    .type = DIV_T_NATURE,
    .range_from = 1,  /* reserve H_CLK divsor 1 */
    .range_to = 3,
    .reg = &divbit_H_CLK,
};

Not sure why divisor 1 has been reserved..

Thanks,
Cristi

Rest looks good to me.

Thanks,
Mani

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