Re: [PATCH 4/5] clk: qcom: Add A7 PLL support

[PATCH 0/5] Add APCS support for SDX55 · Manivannan Sadhasivam <hidden> · 2021-01-04
[PATCH 2/5] mailbox: qcom: Add support for SDX55 APCS IPC · Manivannan Sadhasivam <hidden> · 2021-01-04
[PATCH 3/5] dt-bindings: clock: Add Qualcomm A7 PLL binding · Manivannan Sadhasivam <hidden> · 2021-01-04
[PATCH 1/5] dt-bindings: mailbox: Add binding for SDX55 APCS · Manivannan Sadhasivam <hidden> · 2021-01-04
[PATCH 4/5] clk: qcom: Add A7 PLL support · Manivannan Sadhasivam <hidden> · 2021-01-04
Re: [PATCH 4/5] clk: qcom: Add A7 PLL support · Konrad Dybcio <hidden> · 2021-01-04
Re: [PATCH 4/5] clk: qcom: Add A7 PLL support · Manivannan Sadhasivam <hidden> · 2021-01-08
[PATCH 5/5] clk: qcom: Add SDX55 APCS clock controller support · Manivannan Sadhasivam <hidden> · 2021-01-04

From: Konrad Dybcio <hidden>
Date: 2021-01-04 15:31:33
Also in: linux-arm-msm, linux-clk, lkml

Hi,

could you explicitly state in the probe function (or just in the driver in general, as there's not much more?) and the config structs that the target SoC is X55?

A few more SoCs (MDM9607, MSM8x26 and some others) also use what's known as "A7PLL" downstream, but all of them have a separate configuration for their specific PLLs, which aren't compatible with each other.


Konrad

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