[PATCH 2/5] mailbox: qcom: Add support for SDX55 APCS IPC
From: Manivannan Sadhasivam <hidden>
Date: 2021-01-04 08:13:02
Also in:
linux-arm-msm, linux-clk, lkml
Subsystem:
arm/qualcomm mailing list, mailbox api, the rest · Maintainers:
Jassi Brar, Linus Torvalds
In SDX55, the IPC bits are located in the APCS GCC block. Also, this block can provide clock functionality. Hence, add support for IPC with correct offset and name of the clock provider. Signed-off-by: Manivannan Sadhasivam <redacted> --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 077e5c6a9ef7..b00556450335 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c@@ -61,6 +61,10 @@ static const struct qcom_apcs_ipc_data apps_shared_apcs_data = { .offset = 12, .clk_name = NULL }; +static const struct qcom_apcs_ipc_data sdx55_apcs_data = { + .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" +}; + static const struct regmap_config apcs_regmap_config = { .reg_bits = 32, .reg_stride = 4,
@@ -162,6 +166,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,sdm660-apcs-hmss-global", .data = &sdm660_apcs_data }, { .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, + { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
--
2.25.1