Re: [PATCH v2 09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM
From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date: 2020-05-04 14:20:46
Also in:
dmaengine, linux-gpio, linux-mmc, linux-renesas-soc, linux-serial, lkml
Hi Geert, Thank you for the review. On Mon, May 4, 2020 at 2:01 PM Geert Uytterhoeven [off-list ref] wrote:
Hi Prabhakar, On Sun, May 3, 2020 at 11:48 PM Lad Prabhakar [off-list ref] wrote:quoted
Add support for iWave RZ/G1H Qseven System On Module. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <redacted>Thanks for your patch!quoted
--- /dev/null +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi@@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave RZ/G1H Qseven SOM + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a7742.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "iwave,g21m", "renesas,r8a7742"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x20000000>;According to the schematics, the second bank is also 1 GiB, so the reg length should be 0x40000000.
Agreed will fix that.
quoted
+ };quoted
+&pfc { + mmc1_pins: mmc1 { + groups = "mmc1_data4", "mmc1_ctrl"; + function = "mmc1"; + }; +}; + +&mmcif1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <4>; + non-removable; + status = "okay"; +};The eMMC has an 8-bit data path. Is there any specific reason you use bus-width = <4>, and the "mmc1_data4" pin group?
MMC1_DATA7 is shared with VI1_CLK, so instead of limiting to only one device when using 8-bit just switched to 4bit mode so that both the peripherals can be used. Cheers, --Prabhakar
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
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