-----Original Message-----
From: Marc Zyngier <maz@kernel.org>
Sent: 12 November 2019 18:28
To: Yash Shah <redacted>
Cc: linus.walleij@linaro.org; bgolaszewski@baylibre.com;
robh+dt@kernel.org; mark.rutland@arm.com; palmer@dabbelt.com; Paul
Walmsley ( Sifive) [off-list ref]; aou@eecs.berkeley.edu;
tglx@linutronix.de; jason@lakedaemon.net; bmeng.cn@gmail.com;
atish.patra@wdc.com; Sagar Kadam [off-list ref]; linux-
gpio@vger.kernel.org; devicetree@vger.kernel.org; linux-
riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Sachin Ghadi
[off-list ref]
Subject: Re: [PATCH 3/4] gpio: sifive: Add GPIO driver for SiFive SoCs

On 2019-11-12 13:21, Yash Shah wrote:

quoted

Adds the GPIO driver for SiFive RISC-V SoCs.

Signed-off-by: Wesley W. Terpstra <redacted>
[Atish: Various fixes and code cleanup]
Signed-off-by: Atish Patra <redacted>
Signed-off-by: Yash Shah <redacted>

[...]

quoted

+static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
+					     unsigned int child,
+					     unsigned int child_type,
+					     unsigned int *parent,
+					     unsigned int *parent_type)
+{
+	/* All these interrupts are level high in the CPU */
+	*parent_type = IRQ_TYPE_LEVEL_HIGH;

It is bizare that you enforce LEVEL_HIGH here, while setting it to NONE in the
PLIC driver. These things should be consistent.

Will change this to IRQ_TYPE_NONE.

quoted

+	*parent = child + 7;

Irk, magic numbers...

This is the offset for GPIO IRQs. Will add a macro for this.
Thanks for your comments!

- Yash