On Fri, Aug 16, 2019 at 08:46:11PM -0700, Stephen Boyd wrote:

Quoting Manivannan Sadhasivam (2019-08-16 20:34:22)

quoted

On Wed, Aug 07, 2019 at 10:01:28PM -0700, Stephen Boyd wrote:

quoted

Quoting Manivannan Sadhasivam (2019-07-05 08:14:36)

quoted

+It is expected that it is defined using standard clock bindings as "osc".
+
+Example: 
+
+        clk: clock-controller@800 {
+                compatible = "bitmain,bm1880-clk";
+                reg = <0xe8 0x0c>,<0x800 0xb0>;

It looks weird still. What hardware module is this actually part of?
Some larger power manager block?

These are all part of the sysctrl block (clock + pinctrl + reset) and the
register domains got split between system and pll.

And that can't be one node that probes the clk, pinctrl, and reset
drivers from C code?

It is not a MFD for sure. It's just grouping of the register domains together.

Thanks,
Mani