[PATCH 07/14] serial: tegra: add compatible for new chips
From: Krishna Yarlagadda <hidden>
Date: 2019-08-12 11:29:07
Also in:
linux-serial, linux-tegra, lkml
Subsystem:
open firmware and flattened device tree bindings, the rest, tty layer and serial drivers · Maintainers:
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds, Greg Kroah-Hartman, Jiri Slaby
Add new compatible string for Tegra186. It differs from earlier chips as it has fifo mode enable check and 8 byte dma buffer. Add new compatible string for Tegra194. Tegra194 has different error tolerance levels for baud rate compared to older chips. Signed-off-by: Krishna Yarlagadda <redacted> --- Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
index d7edf73..187ec78 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt@@ -1,7 +1,8 @@ NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver. Required properties: -- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". +- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart", + nvidia,tegra186-hsuart, nvidia,tegra194-hsuart. - reg: Should contain UART controller registers location and length. - interrupts: Should contain UART controller interrupts. - clocks: Must contain one entry, for the module clock.
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2.7.4