[PATCH v3 0/4] Improve VCHIQ cache line size handling · Phil Elwell <hidden> · 2018-09-17
[PATCH v3 1/4] staging/vc04_services: Use correct cache line size · Phil Elwell <hidden> · 2018-09-17
Re: [PATCH v3 1/4] staging/vc04_services: Use correct cache line size · Stefan Wahren <hidden> · 2018-09-23
[PATCH v3 2/4] dt-bindings: soc: Document "brcm,bcm2836-vchiq" · Phil Elwell <hidden> · 2018-09-17
Re: [PATCH v3 2/4] dt-bindings: soc: Document "brcm,bcm2836-vchiq" · Rob Herring <robh@kernel.org> · 2018-09-26
[PATCH v3 3/4] ARM: dts: bcm283x: Correct vchiq compatible string · Phil Elwell <hidden> · 2018-09-17
[PATCH v3 4/4] ARM: dts: bcm283x: Correct mailbox register sizes · Phil Elwell <hidden> · 2018-09-17
Re: [PATCH v3 0/4] Improve VCHIQ cache line size handling · Stefan Wahren <hidden> · 2018-09-17
Re: [PATCH v3 0/4] Improve VCHIQ cache line size handling · Phil Elwell <hidden> · 2018-09-17
Re: [PATCH v3 0/4] Improve VCHIQ cache line size handling · Florian Fainelli <f.fainelli@gmail.com> · 2018-09-17
Re: [PATCH v3 0/4] Improve VCHIQ cache line size handling · Phil Elwell <hidden> · 2018-09-17
Re: [PATCH v3 0/4] Improve VCHIQ cache line size handling · Stefan Wahren <hidden> · 2018-11-06

Re: [PATCH v3 1/4] staging/vc04_services: Use correct cache line size

From: Stefan Wahren <hidden>
Date: 2018-09-23 15:24:50
Also in: linux-arm-kernel

Phil Elwell [off-list ref] hat am 17. September 2018 um 10:22 geschrieben:


Use the compatible string in the DTB to select the correct cache line
size for the SoC - 32 for BCM2835, and 64 for BCM2836 and BCM2837.

Signed-off-by: Phil Elwell <redacted>

Tested-by: Stefan Wahren <redacted>

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