[PATCH v4 5/7] i2c: designware: add MSCC Ocelot support
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
Date: 2018-08-16 08:45:51
Also in:
linux-i2c, linux-mips, lkml
Subsystem:
i2c subsystem, i2c subsystem host drivers, synopsys designware i2c driver, the rest · Maintainers:
Andi Shyti, Mika Westerberg, Linus Torvalds
The Microsemi Ocelot I2C controller is a designware IP. It also has a second set of registers to allow tweaking SDA hold time and spike filtering. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> --- drivers/i2c/busses/i2c-designware-core.h | 3 ++ drivers/i2c/busses/i2c-designware-platdrv.c | 40 +++++++++++++++++++++ 2 files changed, 43 insertions(+)
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index ad4e9619d365..f7883224e1af 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h@@ -238,6 +238,7 @@ struct dw_i2c_dev { struct device *dev; void __iomem *base; + void __iomem *ext; struct completion cmd_complete; struct clk *clk; struct reset_control *rst;
@@ -292,6 +293,8 @@ struct dw_i2c_dev { #define ACCESS_INTR_MASK 0x00000004 #define MODEL_CHERRYTRAIL 0x00000100 +#define MODEL_MSCC_OCELOT 0x00000200 +#define MODEL_MASK 0x00000f00 u32 dw_readl(struct dw_i2c_dev *dev, int offset); void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset);
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 776d4354f366..0d9bfa45550d 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c@@ -170,11 +170,48 @@ static inline int dw_i2c_acpi_configure(struct platform_device *pdev) #endif #ifdef CONFIG_OF +#define MSCC_ICPU_CFG_TWI_DELAY 0x0 +#define MSCC_ICPU_CFG_TWI_DELAY_ENABLE BIT(0) +#define MSCC_ICPU_CFG_TWI_SPIKE_FILTER 0x4 + +static int mscc_twi_set_sda_hold_time(struct dw_i2c_dev *dev) +{ + writel((dev->sda_hold_time << 1) | MSCC_ICPU_CFG_TWI_DELAY_ENABLE, + dev->ext + MSCC_ICPU_CFG_TWI_DELAY); + + return 0; +} + +int dw_i2c_of_configure(struct platform_device *pdev) +{ + struct dw_i2c_dev *dev = platform_get_drvdata(pdev); + struct resource *mem; + + switch (dev->flags & MODEL_MASK) { + case MODEL_MSCC_OCELOT: + mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); + dev->ext = devm_ioremap_resource(&pdev->dev, mem); + if (!IS_ERR(dev->ext)) + dev->set_sda_hold_time = mscc_twi_set_sda_hold_time; + break; + default: + break; + } + + return 0; +} + static const struct of_device_id dw_i2c_of_match[] = { { .compatible = "snps,designware-i2c", }, + { .compatible = "mscc,ocelot-i2c", .data = (void *)MODEL_MSCC_OCELOT }, {}, }; MODULE_DEVICE_TABLE(of, dw_i2c_of_match); +#else +static inline int dw_i2c_of_configure(struct platform_device *pdev) +{ + return -ENODEV; +} #endif static void i2c_dw_configure_master(struct dw_i2c_dev *dev)
@@ -309,6 +346,9 @@ static int dw_i2c_plat_probe(struct platform_device *pdev) dev->flags |= (uintptr_t)device_get_match_data(&pdev->dev); + if (pdev->dev.of_node) + dw_i2c_of_configure(pdev); + if (has_acpi_companion(&pdev->dev)) dw_i2c_acpi_configure(pdev);
--
2.18.0