From: Vignesh R <vigneshr@ti.com> Date: 2018-06-27 12:43:55
Make workaround for errata i870 applicable in Host mode as
well(previously it was enabled only for EP mode) as per errata
documentation: http://www.ti.com/lit/er/sprz450/sprz450.pdf
Tested on DRA72 EVM
Changes since v1:
Drop IRQ handling rework (will be sent out separately)
v1: https://lkml.org/lkml/2017/12/1/59
Vignesh R (4):
dt-bindings: PCI: dra7xx: Add bindings for unaligned access in host
mode
pci: dwc: pci-dra7xx: Enable errata i870 for both EP and RC mode
ARM: dts: dra7: Enable workaround for errata i870 in PCIe host mode
ARM: dts: dra7: Fix up unaligned access setting for PCIe EP
Documentation/devicetree/bindings/pci/ti-pci.txt | 5 +++++
arch/arm/boot/dts/dra7.dtsi | 4 +++-
drivers/pci/controller/dwc/pci-dra7xx.c | 12 ++++++------
3 files changed, 14 insertions(+), 7 deletions(-)
--
2.18.0
From: Vignesh R <vigneshr@ti.com> Date: 2018-06-27 14:02:26
Errata i870 is applicable in both EP and RC mode. Therefore rename
function dra7xx_pcie_ep_unaligned_memaccess(), that implements errata
workaround, to dra7xx_pcie_unaligned_memaccess() and call it from a
common place. So, that errata workaround is applied for both modes of
operation.
Reported-by: Chris Welch <redacted>
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
drivers/pci/controller/dwc/pci-dra7xx.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
From: Vignesh R <vigneshr@ti.com> Date: 2018-06-27 14:59:16
Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
incorrectly documented in the TRM. In fact, the bit positions are
swapped. Update the DT bindings for PCIe EP to reflect the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Vignesh R <vigneshr@ti.com> Date: 2018-06-27 14:59:21
Update device tree binding documentation of TI's dra7xx PCI controller
for enabling unaligned mem access as applicable not just in EP mode but
in host mode as well.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 5 +++++
1 file changed, 5 insertions(+)
@@ -26,6 +26,11 @@ HOST MODE ranges, interrupt-map-mask, interrupt-map : as specified in ../designware-pcie.txt+ - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument+ should contain the register offset within syscon+ and the 2nd argument should contain the bit field+ for setting the bit to enable unaligned+ access. DEVICE MODE ===========
From: Vignesh R <vigneshr@ti.com> Date: 2018-06-27 14:59:45
Add ti,syscon-unaligned-access property to PCIe RC nodes to set
appropriate bits in CTRL_CORE_SMA_SW_7 register to enable workaround for
errata i870.
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 2 ++
1 file changed, 2 insertions(+)
From: Kishon Vijay Abraham I <hidden> Date: 2018-07-17 09:54:48
On Wednesday 27 June 2018 05:59 PM, Vignesh R wrote:
Errata i870 is applicable in both EP and RC mode. Therefore rename
function dra7xx_pcie_ep_unaligned_memaccess(), that implements errata
workaround, to dra7xx_pcie_unaligned_memaccess() and call it from a
common place. So, that errata workaround is applied for both modes of
operation.
Reported-by: Chris Welch <redacted>
Signed-off-by: Vignesh R <vigneshr@ti.com>
From: Kishon Vijay Abraham I <hidden> Date: 2018-07-17 09:56:04
On Wednesday 27 June 2018 05:59 PM, Vignesh R wrote:
Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
incorrectly documented in the TRM. In fact, the bit positions are
swapped. Update the DT bindings for PCIe EP to reflect the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Shouldn't this be sent to stable fixes?
Thanks
Kishon
From: Lorenzo Pieralisi <hidden> Date: 2018-07-18 11:00:58
On Wed, Jun 27, 2018 at 05:59:17PM +0530, Vignesh R wrote:
quoted hunk
Errata i870 is applicable in both EP and RC mode. Therefore rename
function dra7xx_pcie_ep_unaligned_memaccess(), that implements errata
workaround, to dra7xx_pcie_unaligned_memaccess() and call it from a
common place. So, that errata workaround is applied for both modes of
operation.
Reported-by: Chris Welch <redacted>
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
drivers/pci/controller/dwc/pci-dra7xx.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
@@ -695,6 +695,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)if(dra7xx->link_gen<0||dra7xx->link_gen>2)dra7xx->link_gen=2;+ret=dra7xx_pcie_unaligned_memaccess(dev);+if(ret)+dev_err(dev,"WA for Errata i870 not appplied. Update DT\n");
Hi Vignesh,
Nit: s/appplied/applied
Two questions:
- Current code applies the unaligned_memaccess() workaround for all
compatible variants. This is fine for current controllers (since
they are all affected), the code path above will have to be
reworked if there is any other compatible IP re-using the driver
that does not require the workaround.
- How do you want this series to go upstream ? If it goes via arm-soc,
which I think it should, here is my ACK on this patch:
Acked-by: Lorenzo Pieralisi <redacted>
Please let me know if I can drop this series from the PCI patchwork.
Thanks,
Lorenzo
quoted hunk
+ switch (mode) { case DW_PCIE_RC_TYPE: if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
@@ -717,10 +721,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, DEVICE_TYPE_EP);- ret = dra7xx_pcie_ep_unaligned_memaccess(dev);- if (ret)- goto err_gpio;- ret = dra7xx_add_pcie_ep(dra7xx, pdev); if (ret < 0) goto err_gpio;
From: Vignesh R <vigneshr@ti.com> Date: 2018-07-19 10:33:57
Hi Lorenzo,
On Wednesday 18 July 2018 04:32 PM, Lorenzo Pieralisi wrote:
On Wed, Jun 27, 2018 at 05:59:17PM +0530, Vignesh R wrote:
quoted
Errata i870 is applicable in both EP and RC mode. Therefore rename
function dra7xx_pcie_ep_unaligned_memaccess(), that implements errata
workaround, to dra7xx_pcie_unaligned_memaccess() and call it from a
common place. So, that errata workaround is applied for both modes of
operation.
Reported-by: Chris Welch <redacted>
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
drivers/pci/controller/dwc/pci-dra7xx.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
@@ -695,6 +695,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)if(dra7xx->link_gen<0||dra7xx->link_gen>2)dra7xx->link_gen=2;+ret=dra7xx_pcie_unaligned_memaccess(dev);+if(ret)+dev_err(dev,"WA for Errata i870 not appplied. Update DT\n");
Hi Vignesh,
Nit: s/appplied/applied
Oops, let me know if you want me to resend with this fixed.
Two questions:
- Current code applies the unaligned_memaccess() workaround for all
compatible variants. This is fine for current controllers (since
they are all affected), the code path above will have to be
reworked if there is any other compatible IP re-using the driver
that does not require the workaround.
There are no compatible IPs that don't require this workaround. Also, I
don't see this IP being re-used in future. If you insist, I can add a
errata flag
- How do you want this series to go upstream ? If it goes via arm-soc,
which I think it should, here is my ACK on this patch:
Patch 1 and 2(dt bindings update and driver patch) can go in via PCI
tree. And DT changes(patch 3 and 4) can be picked up by Tony via
omap/arm-soc tree. They are mostly independent and should not cause any
problems. Does that sound good?
Acked-by: Lorenzo Pieralisi <redacted>
Thanks!
Please let me know if I can drop this series from the PCI patchwork.
Thanks,
Lorenzo
quoted
+ switch (mode) { case DW_PCIE_RC_TYPE: if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
@@ -717,10 +721,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, DEVICE_TYPE_EP);- ret = dra7xx_pcie_ep_unaligned_memaccess(dev);- if (ret)- goto err_gpio;- ret = dra7xx_add_pcie_ep(dra7xx, pdev); if (ret < 0) goto err_gpio;
From: Vignesh R <vigneshr@ti.com> Date: 2018-07-19 10:53:51
Hi Tony,
On Tuesday 17 July 2018 03:25 PM, Kishon Vijay Abraham I wrote:
On Wednesday 27 June 2018 05:59 PM, Vignesh R wrote:
quoted
Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
incorrectly documented in the TRM. In fact, the bit positions are
swapped. Update the DT bindings for PCIe EP to reflect the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Shouldn't this be sent to stable fixes?
This patch fixes:
Fixes: d23f3839fe97 ("ARM: dts: DRA7: Add pcie1 dt node for EP mode")
Cc: stable@vger.kernel.org
let me know if this needs to be resent with Fixes tag.
Regards
Vignesh
From: Lorenzo Pieralisi <hidden> Date: 2018-07-19 11:16:03
On Thu, Jul 19, 2018 at 04:04:34PM +0530, Vignesh R wrote:
Hi Lorenzo,
On Wednesday 18 July 2018 04:32 PM, Lorenzo Pieralisi wrote:
quoted
On Wed, Jun 27, 2018 at 05:59:17PM +0530, Vignesh R wrote:
quoted
Errata i870 is applicable in both EP and RC mode. Therefore rename
function dra7xx_pcie_ep_unaligned_memaccess(), that implements errata
workaround, to dra7xx_pcie_unaligned_memaccess() and call it from a
common place. So, that errata workaround is applied for both modes of
operation.
Reported-by: Chris Welch <redacted>
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
drivers/pci/controller/dwc/pci-dra7xx.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
@@ -695,6 +695,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)if(dra7xx->link_gen<0||dra7xx->link_gen>2)dra7xx->link_gen=2;+ret=dra7xx_pcie_unaligned_memaccess(dev);+if(ret)+dev_err(dev,"WA for Errata i870 not appplied. Update DT\n");
Hi Vignesh,
Nit: s/appplied/applied
Oops, let me know if you want me to resend with this fixed.
I can fix it, no problem but see below.
quoted
Two questions:
- Current code applies the unaligned_memaccess() workaround for all
compatible variants. This is fine for current controllers (since
they are all affected), the code path above will have to be
reworked if there is any other compatible IP re-using the driver
that does not require the workaround.
There are no compatible IPs that don't require this workaround. Also, I
don't see this IP being re-used in future. If you insist, I can add a
errata flag
I do not insist, I just pointed this out ;-)
quoted
- How do you want this series to go upstream ? If it goes via arm-soc,
which I think it should, here is my ACK on this patch:
Patch 1 and 2(dt bindings update and driver patch) can go in via PCI
tree. And DT changes(patch 3 and 4) can be picked up by Tony via
omap/arm-soc tree. They are mostly independent and should not cause any
problems. Does that sound good?
It should be fine but technically as soon as patch (2) is applied we
would have a regression if patches (3) and (4) are applied separately.
You could re-order the series and send everything via arm-soc.
It is not such a big deal, your choice, please let me know.
Thanks,
Lorenzo
quoted
Acked-by: Lorenzo Pieralisi <redacted>
Thanks!
quoted
Please let me know if I can drop this series from the PCI patchwork.
Thanks,
Lorenzo
quoted
+ switch (mode) { case DW_PCIE_RC_TYPE: if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
@@ -717,10 +721,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, DEVICE_TYPE_EP);- ret = dra7xx_pcie_ep_unaligned_memaccess(dev);- if (ret)- goto err_gpio;- ret = dra7xx_add_pcie_ep(dra7xx, pdev); if (ret < 0) goto err_gpio;
From: Vignesh R <vigneshr@ti.com> Date: 2018-07-19 15:58:25
On Thursday 19 July 2018 04:45 PM, Lorenzo Pieralisi wrote:
On Thu, Jul 19, 2018 at 04:04:34PM +0530, Vignesh R wrote:
quoted
Hi Lorenzo,
[...]
quoted
quoted
quoted
+ ret = dra7xx_pcie_unaligned_memaccess(dev);+ if (ret)+ dev_err(dev, "WA for Errata i870 not appplied. Update DT\n");
Hi Vignesh,
Nit: s/appplied/applied
Oops, let me know if you want me to resend with this fixed.
I can fix it, no problem but see below.
quoted
quoted
Two questions:
- Current code applies the unaligned_memaccess() workaround for all
compatible variants. This is fine for current controllers (since
they are all affected), the code path above will have to be
reworked if there is any other compatible IP re-using the driver
that does not require the workaround.
There are no compatible IPs that don't require this workaround. Also, I
don't see this IP being re-used in future. If you insist, I can add a
errata flag
I do not insist, I just pointed this out ;-)
quoted
quoted
- How do you want this series to go upstream ? If it goes via arm-soc,
which I think it should, here is my ACK on this patch:
Patch 1 and 2(dt bindings update and driver patch) can go in via PCI
tree. And DT changes(patch 3 and 4) can be picked up by Tony via
omap/arm-soc tree. They are mostly independent and should not cause any
problems. Does that sound good?
It should be fine but technically as soon as patch (2) is applied we
would have a regression if patches (3) and (4) are applied separately.
Right, although not a regression, I see your point. It would be good to
merge patch 3 and 4 before patch 2.
Tony,
Let me know if you are okay with taking this series via omap tree. I can
resend re-ordering patch 2 to come at the end of the series.
Regards
Vignesh
quoted
quoted
Acked-by: Lorenzo Pieralisi <redacted>
Thanks!
quoted
Please let me know if I can drop this series from the PCI patchwork.
Thanks,
Lorenzo
quoted
+ switch (mode) { case DW_PCIE_RC_TYPE: if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
@@ -717,10 +721,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, DEVICE_TYPE_EP);- ret = dra7xx_pcie_ep_unaligned_memaccess(dev);- if (ret)- goto err_gpio;- ret = dra7xx_add_pcie_ep(dra7xx, pdev); if (ret < 0) goto err_gpio;