Hi Bjorn,
Thanks for the review.

On 03/19/2018 04:15 AM, Bjorn Andersson wrote:

On Wed 14 Mar 02:21 PDT 2018, Sibi S wrote:

quoted

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 7fc7769..d06bd1d 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig

@@ -81,6 +81,16 @@ config RESET_PISTACHIO
  	help
  	  This enables the reset driver for ImgTec Pistachio SoCs.
  
+config RESET_QCOM_AOSS
+	bool "Qcom AOSS Reset Driver"
+	depends on ARCH_QCOM || COMPILE_TEST
+	select MFD_SYSCON

Drop syscon

will drop it

quoted

+	help
+	  This enables the AOSS (always on subsystem) reset driver
+	  for Qualcomm SDM845 SoCs. Say Y if you want to control
+	  reset signals provided by AOSS for Modem, Venus, ADSP,
+	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
+

[..]

quoted

diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c

[..]

quoted

+static const struct regmap_config sdm845_aoss_regmap_config = {
+	.name		= "aoss-reset",
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	.max_register	= 0x20000,
+	.fast_io	= true,
+};

Is there a particular reason why you're setting up a regmap and not just
operate on the ioremap region directly with readl/writel? It would save
you a few lines of code and some runtime memory.

The idea here is to reuse the driver in modified configuration as
pdc_sync restart controller which is to be used for adsp_pil. PDC sync
reset register is a single register with multiple reset lines hence
would warrant setting up a regmap. I can remove these changes and add
them when I add pdc_sync reset controller though.

quoted

+
+static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = {
+	[AOSS_CC_MSS_RESTART] = { 0x0, 0 },
+	[AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 },
+	[AOSS_CC_VENUS_RESTART] = { 0x2000, 0 },
+	[AOSS_CC_GPU_RESTART] = { 0x3000, 0 },
+	[AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 },
+	[AOSS_CC_WCSS_RESTART] = { 0x10000, 0 },
+	[AOSS_CC_LPASS_RESTART] = { 0x20000, 0 },

Do you have a case where bit != 0? If not please drop the bit until it's
necessary.

had the bit variable for the above state reason.

quoted

+};
+
+static const struct qcom_aoss_desc sdm845_aoss_desc = {
+	.config = &sdm845_aoss_regmap_config,
+	.resets = sdm845_aoss_resets,
+	/* Wait 6 32kHz sleep cycles for reset */
+	.delay = 200,

Please move this constant into qcom_aoss_control_reset(), until there's
a need for it to be configurable.

quoted

+	.num_resets = ARRAY_SIZE(sdm845_aoss_resets),
+};
+

[..]

quoted

+static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
+					unsigned long idx)
+{
+	struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+	int ret;
+
+	ret = qcom_aoss_control_assert(rcdev, idx);
+	if (ret)
+		return ret;
+
+	udelay(data->desc->delay);

Per Documentation/timers/timers-howto.txt please use usleep_range() when
delays are between 10us and 20ms.

will replace them

quoted

+
+	return qcom_aoss_control_deassert(rcdev, idx);
+}

Regards,
Bjorn

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