Re: [PATCH v2 1/6] phy: qcom-qmp: Enable pipe_clk before checking USB3 PHY_STATUS

fed back to QMP PHY and is output from PHY only after PHY is reset
and initialized, hence it can't be enabled too early in initialization
sequence.

Signed-off-by: Manu Gautam <redacted>
---
 drivers/phy/qualcomm/phy-qcom-qmp.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 6470c5d..73aa282 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c

@@ -797,8 +797,13 @@ static int qcom_qmp_phy_poweron(struct phy *phy)
 {
        struct qmp_phy *qphy = phy_get_drvdata(phy);
        struct qcom_qmp *qmp = qphy->qmp;
+       const struct qmp_phy_cfg *cfg = qmp->cfg;
        int ret;
 
+       /* Not needed for USB3 PHY as pipe_clk is enabled from phy_init */
+       if (cfg->type == PHY_TYPE_USB3)
+               return 0;

+
        ret = clk_prepare_enable(qphy->pipe_clk);
        if (ret)
                dev_err(qmp->dev, "pipe_clk enable failed, err=%d\n", ret);

@@ -1008,6 +1013,19 @@ static int qcom_qmp_phy_init(struct phy *phy)
        status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
        mask = cfg->mask_pcs_ready;
 
+       /* USB3 PHY requires pipe_clk for PLL lock and calibration */
+       if (cfg->type == PHY_TYPE_USB3) {
+               ret = clk_prepare_enable(qphy->pipe_clk);
+               if (ret)
+                       dev_err(qmp->dev, "pipe_clk enable err=%d\n", ret);
+               /*
+                * Ignore this error as pipe_clk might take some time to get
+                * enabled. In any case following check for PHY PLL lock would
+                * timeout below if there is a fatal error and clock is not fed
+                * to PHY
+                */
+