[PATCH v2 6/7] dt-bindings: serial: Add bindings for GENI based UART Controller
From: Karthikeyan Ramasubramanian <hidden>
Date: 2018-01-13 01:05:46
Also in:
linux-arm-msm, linux-i2c, linux-serial
Subsystem:
arm/qualcomm mailing list, arm/qualcomm support, open firmware and flattened device tree bindings, the rest, tty layer and serial drivers · Maintainers:
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds, Greg Kroah-Hartman, Jiri Slaby
Add device tree binding support for GENI based UART Controller in the QUP Wrapper. Signed-off-by: Karthikeyan Ramasubramanian <redacted> Signed-off-by: Girish Mahadevan <redacted> --- .../devicetree/bindings/serial/qcom,geni-uart.txt | 29 ++++++++++++++++++++++ .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 13 ++++++++++ 2 files changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
diff --git a/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
new file mode 100644
index 0000000..e7b9e24
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt@@ -0,0 +1,29 @@ +Qualcomm Technologies Inc. GENI Serial Engine based UART Controller + +The Generic Interface (GENI) Serial Engine based UART controller supports +console use-cases and is supported only by GENI based Qualcomm Universal +Peripheral (QUP) cores. + +Required properties: +- compatible: should contain "qcom,geni-debug-uart". +- reg: Should contain UART register location and length. +- reg-names: Should contain "se-phys". +- interrupts: Should contain UART core interrupts. +- clock-names: Should contain "se-clk". +- clocks: clocks needed for UART, includes the core clock. +- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names + Should be "active" and "sleep" for the pin confuguration when core is active + or when entering sleep state. + +Example: +uart0: qcom,serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa88000 0x7000>; + reg-names = "se-phys"; + interrupts = <0 355 0>; + clock-names = "se-clk"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_uart_3_active>; + pinctrl-1 = <&qup_1_uart_3_sleep>; +};
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
index 2ffbb3e..c307788 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt@@ -26,6 +26,7 @@ controller, spi controller, or some combination of aforementioned devices. See the following documentation for child node definitions: Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt +Documentation/devicetree/bindings/serial/qcom,geni-uart.txt Example: qup0: qcom,geniqup0@8c0000 {
@@ -50,4 +51,16 @@ Example: #address-cells = <1>; #size-cells = <0>; }; + + uart0: qcom,serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa88000 0x7000>; + reg-names = "se-phys"; + interrupts = <0 355 0>; + clock-names = "se-clk"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_uart_3_active>; + pinctrl-1 = <&qup_1_uart_3_sleep>; + }; }
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