Thread (42 messages) 42 messages, 5 authors, 2018-03-05
STALE3026d
Revisions (2)
  1. v1 current
  2. v1 [diff vs current]

[PATCH 1/7] watchdog: JZ4740: Disable clock after stopping counter

From: Paul Cercueil <paul@crapouillou.net>
Date: 2017-12-28 16:31:30
Also in: linux-mips, linux-watchdog, lkml
Subsystem: ingenic jz47xx socs, the rest, watchdog device drivers · Maintainers: Paul Cercueil, Linus Torvalds, Wim Van Sebroeck, Guenter Roeck

Previously, the clock was disabled first, which makes the watchdog
component insensitive to register writes.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/watchdog/jz4740_wdt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/jz4740_wdt.c b/drivers/watchdog/jz4740_wdt.c
index 20627f22baf6..6955deb100ef 100644
--- a/drivers/watchdog/jz4740_wdt.c
+++ b/drivers/watchdog/jz4740_wdt.c
@@ -124,8 +124,8 @@ static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
 {
 	struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
 
-	jz4740_timer_disable_watchdog();
 	writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
+	jz4740_timer_disable_watchdog();
 
 	return 0;
 }
-- 
2.11.0
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