From: Kishon Vijay Abraham I <hidden> Date: 2017-12-19 08:58:42
Previous version of this series can be found here @ [1]
Patch series adds support to enable x2 lane mode in dra74/dra76 and
dra72 based boards in pci-dra7xx driver. It introduces new compatible
strings in order to enable x2 lane mode support.
Changes from v1:
*) Added ti prefix to syscon-lane-conf and syscon-lane-sel as
suggested to Rob
*) Merged "PCI: dwc: dra7xx: Add support for SoC specific compatible
strings" and "PCI: dwc: pci-dra7xx: Enable x2 mode support" into
a single patch.
*) Fixed $subject as suggested by Bjorn
*) Added x2 lane mode support for DRA72x
The dts changes and phy changes will be sent as a separate series.
[1] -> https://lkml.org/lkml/2017/10/10/276
Kishon Vijay Abraham I (3):
dt-bindings: PCI: dra7xx: Add SoC specific compatible strings
dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7
PCI: dra7xx: Enable x2 mode support for dra74x, dra76x and dra72x
Documentation/devicetree/bindings/pci/ti-pci.txt | 14 +++-
drivers/pci/dwc/pci-dra7xx.c | 90 ++++++++++++++++++++++++
2 files changed, 102 insertions(+), 2 deletions(-)
--
2.11.0
@@ -13,6 +13,12 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", where <X> is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt+ - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system control+ module and the register offset to specify 1 lane or+ 2 lane.+ - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control+ module and the register offset to specify lane+ selection. HOST MODE =========
From: Kishon Vijay Abraham I <hidden> Date: 2017-12-19 09:03:46
dra74x/dra76x and dra72x has separate compatible strings. Add support
for these compatible strings in pci-dra7xx driver to perform syscon
configurations required to get x2 mode working.
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
drivers/pci/dwc/pci-dra7xx.c | 90 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
@@ -587,6 +628,47 @@ static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev)returnret;}+staticintdra7xx_pcie_configure_two_lane(structdevice*dev,+u32b1co_mode_sel_mask)+{+structdevice_node*np=dev->of_node;+structregmap*pcie_syscon;+unsignedintpcie_reg;++pcie_syscon=syscon_regmap_lookup_by_phandle(np,+"ti,syscon-lane-conf");+if(IS_ERR(pcie_syscon)){+dev_err(dev,"unable to get ti,syscon-lane-conf\n");+return-EINVAL;+}++if(of_property_read_u32_index(np,"ti,syscon-lane-conf",1,+&pcie_reg)){+dev_err(dev,"couldn't get lane configuration reg offset\n");+return-EINVAL;+}++regmap_update_bits(pcie_syscon,pcie_reg,PCIE_1LANE_2LANE_SELECTION,+PCIE_1LANE_2LANE_SELECTION);++pcie_syscon=syscon_regmap_lookup_by_phandle(np,"ti,syscon-lane-sel");+if(IS_ERR(pcie_syscon)){+dev_err(dev,"unable to get ti,syscon-lane-sel\n");+return-EINVAL;+}++if(of_property_read_u32_index(np,"ti,syscon-lane-sel",1,+&pcie_reg)){+dev_err(dev,"couldn't get lane selection reg offset\n");+return-EINVAL;+}++regmap_update_bits(pcie_syscon,pcie_reg,b1co_mode_sel_mask,+PCIE_B1C0_MODE_SEL);++return0;+}+staticint__initdra7xx_pcie_probe(structplatform_device*pdev){u32reg;
@@ -608,6 +690,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)conststructof_device_id*match;conststructdra7xx_pcie_of_data*data;enumdw_pcie_device_modemode;+u32b1co_mode_sel_mask;match=of_match_device(of_match_ptr(of_dra7xx_pcie_match),dev);if(!match)
@@ -615,6 +698,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)data=(structdra7xx_pcie_of_data*)match->data;mode=(enumdw_pcie_device_mode)data->mode;+b1co_mode_sel_mask=data->b1co_mode_sel_mask;dra7xx=devm_kzalloc(dev,sizeof(*dra7xx),GFP_KERNEL);if(!dra7xx)
@@ -673,6 +757,12 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)dra7xx->pci=pci;dra7xx->phy_count=phy_count;+if(phy_count==2){+ret=dra7xx_pcie_configure_two_lane(dev,b1co_mode_sel_mask);+if(ret<0)+gotoerr_link;+}+ret=dra7xx_pcie_enable_phy(dra7xx);if(ret){dev_err(dev,"failed to enable phy\n");
From: Kishon Vijay Abraham I <hidden> Date: 2017-12-19 09:05:04
Add new compatible strings for dra74x SoC (also used by dra76x) and
dra72x. This can be used to perform SoC specific configuration
(like configuring PCIe in x2 lane mode).
Signed-off-by: Kishon Vijay Abraham I <redacted>
Signed-off-by: Sekhar Nori <redacted>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
@@ -1,8 +1,12 @@ TI PCI Controllers PCIe DesignWare Controller- - compatible: Should be "ti,dra7-pcie" for RC- Should be "ti,dra7-pcie-ep" for EP+ - compatible: Should be "ti,dra7-pcie" for RC (deprecated)+ Should be "ti,dra7-pcie-ep" for EP (deprecated)+ Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode+ Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode+ Should be "ti,dra726-pcie-rc" for dra72x in RC mode+ Should be "ti,dra726-pcie-ep" for dra72x in EP mode - phys : list of PHY specifiers (used by generic PHY framework) - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the number of PHYs as specified in *phys* property.
@@ -13,6 +13,12 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", where <X> is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt+ - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system control+ module and the register offset to specify 1 lane or+ 2 lane.+ - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control+ module and the register offset to specify lane+ selection.
Adding a property for every syscon register doesn't really scale and
doesn't work if the register layout changes.
Rob
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@@ -13,6 +13,12 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", where <X> is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt+ - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system control+ module and the register offset to specify 1 lane or+ 2 lane.+ - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control+ module and the register offset to specify lane+ selection.
Adding a property for every syscon register doesn't really scale and
doesn't work if the register layout changes.
The register layout doesn't really change between silicon revisions and for new
SoCs, the phandle and the register offset for that SoC will have to be
populated again.
Having said that, I'm not aware of any other alternative here.
Thanks
Kishon
@@ -13,6 +13,12 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", where <X> is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt+ - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system control+ module and the register offset to specify 1 lane or+ 2 lane.+ - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control+ module and the register offset to specify lane+ selection.
Adding a property for every syscon register doesn't really scale and
doesn't work if the register layout changes.
The register layout doesn't really change between silicon revisions and for new
SoCs, the phandle and the register offset for that SoC will have to be
populated again.
Having said that, I'm not aware of any other alternative here.
Sorry I did not realize this is still open. Sounds like I need to
revert commit 4ece93c020e3 ("ARM: dts: dra7: Add properties to
enable PCIe x2 lane mode"), let me know if that is not the case.
Regards,
Tony
@@ -13,6 +13,12 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", where <X> is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt+ - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system control+ module and the register offset to specify 1 lane or+ 2 lane.+ - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control+ module and the register offset to specify lane+ selection.
Adding a property for every syscon register doesn't really scale and
doesn't work if the register layout changes.
The register layout doesn't really change between silicon revisions and for new
SoCs, the phandle and the register offset for that SoC will have to be
populated again.
And what about SoCs that don't exist yet?
quoted
Having said that, I'm not aware of any other alternative here.
What would you do if you had 20 different syscon registers to
configure? Add 20 properties? No, you would have per SoC functions in
the driver to handle the different cases.
Sorry I did not realize this is still open. Sounds like I need to
revert commit 4ece93c020e3 ("ARM: dts: dra7: Add properties to
enable PCIe x2 lane mode"), let me know if that is not the case.
It's fine, I guess. Keep adding more syscon phandles and then I'll NAK
it (if I remember :)).
Rob
@@ -13,6 +13,12 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", where <X> is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt+ - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system control+ module and the register offset to specify 1 lane or+ 2 lane.+ - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control+ module and the register offset to specify lane+ selection.
Adding a property for every syscon register doesn't really scale and
doesn't work if the register layout changes.
The register layout doesn't really change between silicon revisions and for new
SoCs, the phandle and the register offset for that SoC will have to be
populated again.
And what about SoCs that don't exist yet?
quoted
quoted
Having said that, I'm not aware of any other alternative here.
What would you do if you had 20 different syscon registers to
configure? Add 20 properties? No, you would have per SoC functions in
the driver to handle the different cases.
Ideally these syscon registers would be managed by some Linux
generic framework such as clock/regulator/mux/phy.
But yeah, if that does not work, then setting a SoC specific
configuration function based on the compatible value makes sense
to me.
quoted
Sorry I did not realize this is still open. Sounds like I need to
revert commit 4ece93c020e3 ("ARM: dts: dra7: Add properties to
enable PCIe x2 lane mode"), let me know if that is not the case.
It's fine, I guess. Keep adding more syscon phandles and then I'll NAK
it (if I remember :)).
Already reverted, thanks for the comments.
Regards,
Tony
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@@ -13,6 +13,12 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", where <X> is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt+ - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system control+ module and the register offset to specify 1 lane or+ 2 lane.+ - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control+ module and the register offset to specify lane+ selection.
Adding a property for every syscon register doesn't really scale and
doesn't work if the register layout changes.
The register layout doesn't really change between silicon revisions and for new
SoCs, the phandle and the register offset for that SoC will have to be
populated again.
And what about SoCs that don't exist yet?
quoted
quoted
Having said that, I'm not aware of any other alternative here.
What would you do if you had 20 different syscon registers to
configure? Add 20 properties? No, you would have per SoC functions in
the driver to handle the different cases.
Ideally these syscon registers would be managed by some Linux
generic framework such as clock/regulator/mux/phy.
But yeah, if that does not work, then setting a SoC specific
configuration function based on the compatible value makes sense
to me.
All right. I'll add a function for syscon configuration in pci-dra7xx.
Thanks
Kishon
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From: Lorenzo Pieralisi <hidden> Date: 2018-02-26 10:31:06
On Tue, Dec 19, 2017 at 02:28:23PM +0530, Kishon Vijay Abraham I wrote:
dra74x/dra76x and dra72x has separate compatible strings. Add support
s/has/have
quoted hunk
for these compatible strings in pci-dra7xx driver to perform syscon
configurations required to get x2 mode working.
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
drivers/pci/dwc/pci-dra7xx.c | 90 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
Nit: DT guys are more familiar than me on how this data should be
encoded but maybe bit offset + length can be better ? I do not know, I
have no problem leaving them as masks.
From: Kishon Vijay Abraham I <hidden> Date: 2018-02-28 12:04:46
Hi Lorenzo,
On Monday 26 February 2018 04:00 PM, Lorenzo Pieralisi wrote:
On Tue, Dec 19, 2017 at 02:28:23PM +0530, Kishon Vijay Abraham I wrote:
quoted
dra74x/dra76x and dra72x has separate compatible strings. Add support
s/has/have
quoted
for these compatible strings in pci-dra7xx driver to perform syscon
configurations required to get x2 mode working.
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
drivers/pci/dwc/pci-dra7xx.c | 90 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
Nit: DT guys are more familiar than me on how this data should be
encoded but maybe bit offset + length can be better ? I do not know, I
have no problem leaving them as masks.