On Thu, Mar 23, 2017 at 9:45 PM, Rob Clark [off-list ref] wrote:

On Thu, Mar 23, 2017 at 6:21 PM, Rob Herring [off-list ref] wrote:

quoted

On Tue, Mar 14, 2017 at 11:18:05AM -0400, Rob Clark wrote:

quoted

Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Clark <redacted>
---
 .../devicetree/bindings/iommu/qcom,iommu.txt       | 113 +++++++++++++++++++++
 1 file changed, 113 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt

diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
new file mode 100644
index 0000000..fd5b7fa
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@@ -0,0 +1,113 @@
+* QCOM IOMMU v1 Implementation
+
+Qualcomm "B" family devices which are not compatible with arm-smmu have
+a similar looking IOMMU but without access to the global register space,
+and optionally requiring additional configuration to route context irqs
+to non-secure vs secure interrupt line.
+
+** Required properties:
+
+- compatible       : Should be one of:
+
+                        "qcom,msm8916-iommu"
+
+- clock-names      : Should be a pair of "iface" (required for IOMMUs
+                     register group access) and "bus" (required for
+                     the IOMMUs underlying bus access).
+- clocks           : Phandles for respective clocks described by
+                     clock-names.
+- #address-cells   : must be 1.
+- #size-cells      : must be 1.
+- #iommu-cells     : Must be 1.
+- ranges           : Base address and size of the iommu context banks.
+- qcom,iommu-secure-id  : secure-id.
+
+- List of sub-nodes, one per translation context bank.  Each sub-node
+  has the following required properties:
+
+  - compatible     : Should be one of:
+        - "qcom,msm-iommu-v1-ns"  : non-secure context bank
+        - "qcom,msm-iommu-v1-sec" : secure context bank
+  - reg            : Base address and size of context bank within the iommu
+  - interrupts     : The context fault irq.
+
+** Optional properties:
+
+- reg              : Base address and size of the SMMU local base, should
+                     be only specified if the iommu requires configuration
+                     for routing of context bank irq's to secure vs non-
+                     secure lines.  (Ie. if the iommu contains secure
+                     context banks)
+
+
+** Examples:
+
+     apps_iommu: iommu@1e20000 {
+             #address-cells = <1>;
+             #size-cells = <1>;
+             #iommu-cells = <1>;
+             compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";

You didn't document the fallback above. Maybe just drop it if only a few
chips have this iommu.

not completely sure I understand what you want..

I think more than a few chips.. I suspect it is more like everything
after the last "a" family devices (snapdragon 600?) and before 820..
(well, more or less at least a few years worth of devices, stuff that
seems likely to be able to run an upstream kernel would be 800, 805,
808, 810.. and I guess there are some cut down 6xx and 4xx variants of
those)

Okay, then you just need to list qcom,msm-iommu-v1 above. Something
like 'followed by "qcom,msm-iommu-v1"' at the end of the list of
compatibles.

Rob