Thread (14 messages) 14 messages, 5 authors, 2017-03-02

Re: [PATCH V3 2/7] PM / OPP: Introduce "domain-performance-state" binding to OPP nodes

From: Rajendra Nayak <hidden>
Date: 2017-03-01 07:50:40
Also in: linux-pm, lkml


On 02/28/2017 09:22 PM, Rob Herring wrote:
On Tue, Feb 28, 2017 at 9:14 AM, Ulf Hansson [off-list ref] wrote:
quoted
[...]
quoted
quoted
                                    ---> Parent domain-2 (Contains Perfomance states)
                                    |
                                    |
C.) DeviceX  --->  Parent-domain-1  |
                                    |
                                    |
                                    ---> Parent domain-3 (Contains Perfomance states)
I'm a bit confused. How does a domain have 2 parent domains?
This comes from the early design of the generic PM domain, thus I
assume we have some HW with such complex PM topology. However, I don't
know if it is actually being used.

Moreover, the corresponding DT bindings for "power-domains" parents,
can easily be extended to cover more than one parent. See more in
Documentation/devicetree/bindings/power/power_domain.txt
I could easily see device having 2 power domains. For example a cpu
may have separate domains for RAM/caches and logic. And nesting of
yet the bindings for power-domains (for consumer devices) only allows for
one powerdomain to be associated with a device.
power domains is certainly common, but a power domain being contained
in 2 different parents? I don't even see how that is possible in the
physical design. Now if we're mixing PM and power domains again and
the cpu device is pointing to the cpu PM domain which contains 2 power
domains, then certainly that is possible.

Rob
-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
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