quoted

quoted

 + /* Switch from master mode to slave mode. */
 + func_ctrl_reg_val = aspeed_i2c_read(bus, ASPEED_I2C_FUN_CTRL_REG);
 + func_ctrl_reg_val &= ~ASPEED_I2CD_MASTER_EN;
 + func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN;
 + aspeed_i2c_write(bus, func_ctrl_reg_val, ASPEED_I2C_FUN_CTRL_REG);

Can't the hardware work both as master and slave on the same bus?

The hardware can work as master and slave on the same bus. This is how IPMB over i2c works on Aspeed.

Thanks! Then the driver should support this. Maybe it is an idea to
first upstream the master support and add the slave support
incrementally?

Regards,

   Wolfram