Hi Stephen,

On Tue, Nov 29, 2016 at 4:49 AM, Stephen Boyd [off-list ref] wrote:

On 11/22, Vivek Gautam wrote:

quoted

Qualcomm chipsets have QMP phy controller that provides
support to a number of controller, viz. PCIe, UFS, and USB.
Adding dt binding information for the same.

Signed-off-by: Vivek Gautam <redacted>
Acked-by: Rob Herring <robh@kernel.org>
---

Changes since v1:
 - New patch, forked out of the original driver patch:
   "phy: qcom-qmp: new qmp phy driver for qcom-chipsets"
 - updated bindings to include mem resource as a list of
   offset - length pair for serdes block and for each lane.
 - added a new binding for 'lane-offsets' that contains offsets
   to tx, rx and pcs blocks from each lane base address.

 .../devicetree/bindings/phy/qcom-qmp-phy.txt       | 74 ++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
new file mode 100644
index 0000000..ffb173b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt

@@ -0,0 +1,74 @@
+Qualcomm QMP PHY
+----------------
+
+QMP phy controller supports physical layer functionality for a number of
+controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.

[...]

quoted

+Example:
+     pcie_phy: pciephy@34000 {
+             compatible = "qcom,msm8996-qmp-pcie-phy";
+             reg = <0x034000 0x48f>,
+                     <0x035000 0x5bf>,
+                     <0x036000 0x5bf>,
+                     <0x037000 0x5bf>;
+                             /* tx, rx, pcs */
+             lane-offsets = <0x0 0x200 0x400>;
+             #phy-cells = <1>;
+
+             clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+                     <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
+                     <&rpmcc MSM8996_RPM_SMD_LN_BB_CLK>,
+                     <&gcc GCC_PCIE_CLKREF_CLK>,
+                     <&gcc GCC_PCIE_0_PIPE_CLK>,
+                     <&gcc GCC_PCIE_1_PIPE_CLK>,
+                     <&gcc GCC_PCIE_2_PIPE_CLK>;
+             clock-names = "aux", "cfg_ahb",
+                             "ref_clk_src", "ref_clk",

Does MSM8996_RPM_SMD_LN_BB_CLK supply the clock source for
GCC_PCIE_CLKREF_CLK? Did we mess up the parent/child relationship
in the GCC driver? We may want to fix that so that this node
only references clocks that actually go into the device, instead
of clock parents.

The clock documentations do show that the RPM_SMD_LN_BB_CLK provides
the 19.2 MHz phy clocks via pad. So, like you rightly said we may have to
fix the parents for phy reference clocks for difference phy controllers on 8996.

I will gather some more info on this to discuss it further.


Thanks
Vivek

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