On Wed, Nov 2, 2016 at 10:09 AM, Laxman Dewangan [off-list ref] wrote:

NVIDIA Tegra124 and later SoCs support the multi-voltage level and
low power state of some of its IO pads. The IO pads can work in
the voltage of the 1.8V and 3.3V of IO power rail sources. When IO
interface are not used then IO pads can be configure in low power
state to reduce the power from that IO pads.

On Tegra124, the IO power rail source is auto detected by SoC and hence
it is only require to configure in low power mode if IO pads are not
used.

On T210 onwards, the auto-detection is removed from SoC and hence SW
must configure the PMC register explicitly to set proper voltage in
IO pads based on IO rail power source voltage.

Add DT binding document for detailing the DT properties for
configuring IO pads voltage levels and its power state.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

(...)

+-nvidia,power-source-voltage:  Integer. The voltage level of IO pads. The
+                               valid values are 1.8V and 3.3V. Macros are
+                               defined for these voltage levels in
+                               <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
+                               Use TEGRA_IO_PAD_POWER_SOURCE_1800000UV for 1.8V
+                               Use TEGRA_IO_PAD_POWER_SOURCE_3300000UV for 3.3V
+
+                               All IO pads do not support the 1.8V/3.3V
+                               configurations. Valid values for "pins" are
+                               audio-hv, dmic, gpio, sdmmc1, sdmmc3, spi-hv.

As mentioned in another patch, what is wrong with the standard
power-source binding?

Yours,
Linus Walleij