[PATCH 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
STALE3710d
From: Mirza Krak <hidden>
Date: 2016-08-06 19:40:47
Also in:
linux-arm-kernel, linux-clk, linux-tegra
Subsystem:
common clk framework, tegra clock driver, the rest · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Prashant Gaikwad, Linus Torvalds
Revision v1 of 4 in this series.
Revisions (4)
- v1 current
- v2 [diff vs current]
- v3 [diff vs current]
- v4 [diff vs current]
From: Mirza Krak <redacted> Add TEGRA20_CLK_NOR to init tabel and set default rate to 92 MHz which is max rate. Signed-off-by: Mirza Krak <redacted> --- drivers/clk/tegra/clk-tegra20.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 837e5cb..13d3b5a 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c@@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 }, { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 }, { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 }, + { TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 }, { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 }, { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 }, { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
--
2.1.4