[PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
From: Mirza Krak <hidden>
Date: 2016-11-07 08:30:22
Also in:
linux-clk, linux-devicetree, linux-tegra, lkml
Subsystem:
common clk framework, tegra clock driver, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Peter De Schrijver, Prashant Gaikwad, Linus Torvalds
From: Mirza Krak <redacted> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which is max rate. The maximum rate value of 92 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak <redacted> Tested-by: Marcel Ziswiler <redacted> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board Acked-by: Jon Hunter <jonathanh@nvidia.com> --- Changes in v2: - no changes Changes in v3: - Added comment in commit message where I got the maximum rates from. Changes in V4: - no changes drivers/clk/tegra/clk-tegra20.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 837e5cb..13d3b5a 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c@@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 }, { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 }, { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 }, + { TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 }, { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 }, { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 }, { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 }, --
2.1.4