On Wed, Jul 27, 2016 at 07:01:24PM -0400, Rich Felker wrote:

On Wed, Jul 27, 2016 at 06:31:52PM +0100, Mark Rutland wrote:

quoted

IIUC, that means you *could* implement per-irq masking by having the
CPU's mask value set to 0, and flipping the priority of an IRQ between 0
and 1 to disable/enable.

Though from your prior comments it sounds like for AIC2 writes to the
MMIO priority registers are ignored, so that would not work for AIC2?

Right. The register with 8 4-bit fields only made sense for the setup
with 8 irq lines with variable priority; the aic2 has 64 lines with
static priorities.

Thinking about this a little further, this is a good argument for the
"jcore,aic1" *not* being a valid fallback entry in an AIC2 compatible
list. Anything wanting to rely on this behaviour of AIC1 would be broken
on AIC2.

That being the case, no DT should have "jcore,aic1" for an AIC2 node,
and we can explciitly check for the AIC1 string for AIC1-specific
initialisation code (though regardless, it's worht a comment).

A further curiosity: what static priority values for AIC2 apply to
interrupts? Does it apply 0xf (or some over value) uniformly, or can
AIC2 interrupts potentially have varied priorities?

Thanks,
Mark.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html