[PATCH v6 6/8] arm64, dts: add Juno r2 cpu capacity-dmips-mhz information
From: Juri Lelli <hidden>
Date: 2016-07-19 12:41:39
Also in:
linux-arm-kernel, linux-pm, lkml
Subsystem:
arm/versatile express platform, the rest · Maintainers:
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Linus Torvalds
Add Juno r2 cpu capacity-dmips-mhz bindings information. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <redacted> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <redacted> Cc: Kumar Gala <redacted> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <redacted> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Sudeep Holla <redacted> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Jon Medhurst <redacted> Cc: Olof Johansson <redacted> Cc: Robin Murphy <robin.murphy@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Juri Lelli <redacted> --- Changes from v4: - new patch since Juno r2 dt has been merged --- arch/arm64/boot/dts/arm/juno-r2.dts | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
index 88ecd6182b67..823b614b9a40 100644
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts@@ -90,6 +90,7 @@ next-level-cache = <&A72_L2>; clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; }; A72_1: cpu@1 {
@@ -100,6 +101,7 @@ next-level-cache = <&A72_L2>; clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; }; A53_0: cpu@100 {
@@ -110,6 +112,7 @@ next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <485>; }; A53_1: cpu@101 {
@@ -120,6 +123,7 @@ next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <485>; }; A53_2: cpu@102 {
@@ -130,6 +134,7 @@ next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <485>; }; A53_3: cpu@103 {
@@ -140,6 +145,7 @@ next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <485>; }; A72_L2: l2-cache0 {
--
2.7.0