[PATCH v2 21/22] ARM: dts: dra7x-evm: Provide NAND ready pin
From: Roger Quadros <hidden>
Date: 2015-08-07 09:15:48
Also in:
linux-omap, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
On these boards NAND ready pin status is avilable over GPMC_WAIT0 pin. Read speed increases from 13768 KiB/ to 17246 KiB/s. Write speed was unchanged at 7123 KiB/s. Measured using mtd_speedtest.ko. Signed-off-by: Roger Quadros <redacted> --- arch/arm/boot/dts/dra7-evm.dts | 1 + arch/arm/boot/dts/dra72-evm.dts | 1 + 2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 3fb1ced..b717fd0 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts@@ -575,6 +575,7 @@ reg = <0 0 4>; /* device IO registers */ interrupt-parent = <&crossbar_mpu>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>;
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index fc0677a..c1a3397 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts@@ -387,6 +387,7 @@ */ reg = <0 0 4>; /* device IO registers */ interrupt-parent = <&crossbar_mpu>; + ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>;
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2.1.4