[PATCH v2 12/22] mtd: nand: omap: Update DT binding documentation
From: Roger Quadros <hidden>
Date: 2015-08-07 09:21:45
Also in:
linux-omap, lkml
Subsystem:
memory technology devices (mtd), open firmware and flattened device tree bindings, the rest · Maintainers:
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Add compatible id and interrupts. The NAND interrupts are provided by the GPMC controller node. Signed-off-by: Roger Quadros <redacted> --- Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index fb733c4..253e6de 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt@@ -13,7 +13,11 @@ Documentation/devicetree/bindings/mtd/nand.txt Required properties: - - reg: The CS line the peripheral is connected to + - compatible: "ti,omap2-nand" + - reg: range id (CS number), base offset and length of the + NAND I/O space + - interrupt-parent: must point to gpmc node + - interrupts: gpmc interrupt Optional properties:
@@ -55,20 +59,24 @@ Example for an AM33xx board: gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; - reg = <0x50000000 0x1000000>; + reg = <0x50000000 0x36c>; interrupts = <100>; gpmc,num-cs = <8>; gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; - ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND */ + ranges = <0 0 0x08000000 0x1000000>; /* CS0 space, 16MB */ elm_id = <&elm>; nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, NAND I/O window 4 */ + interrupts = <100>; nand-bus-width = <16>; ti,nand-ecc-opt = "bch8"; ti,nand-xfer-type = "polled"; + interrupt-parent = <&gpmc>; + interrupts = <0>, <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>;
--
2.1.4
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