+ {TEGRA_SWGROUP_AFI, 0x200, 0x204, 0},
+ {TEGRA_SWGROUP_AVPC, 0x200, 0x204, 1},
+ {TEGRA_SWGROUP_DC, 0x200, 0x204, 2},
+ {TEGRA_SWGROUP_DCB, 0x200, 0x204, 3},
+ {TEGRA_SWGROUP_EPP, 0x200, 0x204, 4},
+ {TEGRA_SWGROUP_G2, 0x200, 0x204, 5},
+ {TEGRA_SWGROUP_HC, 0x200, 0x204, 6},
+ {TEGRA_SWGROUP_HDA, 0x200, 0x204, 7},
+ {TEGRA_SWGROUP_ISP, 0x200, 0x204, 8},
+ {TEGRA_SWGROUP_MPCORE, 0x200, 0x204, 9},
+ {TEGRA_SWGROUP_MPCORELP, 0x200, 0x204, 10},
+ {TEGRA_SWGROUP_MPE, 0x200, 0x204, 11},
+ {TEGRA_SWGROUP_NV, 0x200, 0x204, 12},
+ {TEGRA_SWGROUP_NV2, 0x200, 0x204, 13},
+ {TEGRA_SWGROUP_PPCS, 0x200, 0x204, 14},
+ {TEGRA_SWGROUP_VDE, 0x200, 0x204, 16},
+ {TEGRA_SWGROUP_VI, 0x200, 0x204, 17},