On Sat. 19 Jun 2021 à 00:55, Stefan Mätje [off-list ref] wrote:

Am Freitag, den 18.06.2021, 23:27 +0900 schrieb Vincent MAILHOL:

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On Fri. 18 Jun 2021 at 21:44, Marc Kleine-Budde [off-list ref] wrote:

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On 18.06.2021 20:17:51, Vincent MAILHOL wrote:

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I just noticed in the mcp2518fd data sheet:

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bit 14-8 TDCO[6:0]: Transmitter Delay Compensation Offset bits;
Secondary Sample Point (SSP) Two’s complement; offset can be
positive,
zero, or negative.

011 1111 = 63 x TSYSCLK
...
000 0000 = 0 x TSYSCLK
...
111 1111 = –64 x TSYSCLK

Have you takes this into account?

I have not. And I fail to understand what would be the physical
meaning if TDCO is zero or negative.

The mcp25xxfd family data sheet says:

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SSP = TDCV + TDCO

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TDCV indicates the position of the bit start on the RX pin.

If I understand correctly in automatic mode TDCV is measured by the CAN
controller and reflects the transceiver delay.

Yes. I phrased it poorly but this is what I wanted to say. It is
the delay to propagate from the TX pin to the RX pin.

If TDCO = 0 then SSP = TDCV + 0 = TDCV thus the measurement
occurs at the bit start on the RX pin.

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I don't know why you want
to subtract a time from that....

The rest of the relevant registers:

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TDCMOD[1:0]: Transmitter Delay Compensation Mode bits; Secondary Sample
Point (SSP)
10-11 = Auto; measure delay and add TDCO.
01 = Manual; Do not measure, use TDCV + TDCO from register
00 = TDC Disabled

TDCO[6:0]: Transmitter Delay Compensation Offset bits; Secondary Sample
Point (SSP)
Two’s complement; offset can be positive, zero, or negative.
011 1111 = 63 x TSYSCLK
...
000 0000 = 0 x TSYSCLK
...
111 1111 = –64 x TSYSCLK

TDCV[5:0]: Transmitter Delay Compensation Value bits; Secondary Sample
Point (SSP)
11 1111 = 63 x TSYSCLK
...
00 0000 = 0 x TSYSCLK

Aside from the negative TDCO, the rest is standard stuff. We can
note the absence of the TDCF but that's not a blocker.

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If TDCO is zero, the measurement occurs on the bit start when all
the ringing occurs. That is a really bad choice to do the
measurement. If it is negative, it means that you are measuring the
previous bit o_O !?

I don't know...

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Maybe I am missing something but I just do not get it.

I believe you started to implement the mcp2518fd.

No I've just looked into the register description.

OK. For your information, the ETAS ES58x FD devices do not allow
the use of manual mode for TDCV. The microcontroller from
Microchip supports it but ETAS firmware only exposes the
automatic TDCV mode. So it can not be used to test what would
occur if SSP = 0.

I will prepare a patch to allow zero value for both TDCV and
TDCO (I am a bit sad because I prefer the current design, but if
ISO allows it, I feel like I have no choice).  However, I refuse
to allow the negative TDCO value unless someone is able to
explain the rationale.

Hi,

perhaps I can shed some light on the idea why it is a good idea to allow
negative TDC offset values. Therefore I would describe the TDC register
interface of the ESDACC CAN-FD controller of our company (see
https://esd.eu/en/products/esdacc).

Thanks for joining the conversation. I am happy to receive help
from more experts!

Register description of TDC-CAN-FD register (reserved bits not shown):

bits [5..0], RO: TDC Measured (TDCmeas)
        Currently measured TDC value, needs baudrate to be set and CAN traffic

bits [21..16], R/W: TDC offset (TDCoffs)
        Depending on the selected mode (see TDC mode)
        - Auto TDC, automatic mode (default)
                signed offset onto measured TDC (TDCeff = TDCmeas + TDCoffs),
                interpreted as 6-bit two's complement value
        - Manual TDC
                absolute unsigned offset (TDCeff = TDCoffs),
                interpreted as 6-bit unsigned value
        - Other modes
                ignored
        In either case TDC offset is a number of CAN clock cycles.

bits [31..30], R/W: TDC mode
        00 = Auto TDC
        01 = Manual TDC
        10 = reserved
        11 = TDC off

First remark is that you use different naming than what I
witnessed so far in other datasheets. Let me try to give the
equivalences between your device and the struct can_tdc which I
proposed in my patches.

The Left members are ESDACC CAN-FD registers, the right members
are variables from Socket CAN.

** Auto TDC **
TDCoffs = struct can_tdc::tdco

** Manual TDC **
TDCoffs = struct can_tdc::tdcv + struct can_tdc::tdco

In both cases, TDCeff corresponds to the SSP position.

So in automatic mode the goal is to be able to move the real sample point
forward and(!) backward from the measured transmitter delay. Therefore the
TDCoffs is interpreted as 6-bit two's complement value to make negative offsets
possible and to decrease the effective (used) TDCeff below the measured value
TDCmeas.

As far as I have understood our FPGA guy the TDCmeas value is the number of
clock cycles counted from the start of transmitting a dominant bit until the
dominant state reaches the RX pin.

Your definition of TDCmeas is consistent with the definition of
TDCV in socket CAN.

What I miss to understand is what does it mean to subtract from
that TDCmeas/TDCV value. If you subtract from it, it means that
TDCeff/SSP is sampled before the signal reaches the RX
pin. Correct?

During the data phase the sample point is controlled by the tseg values set for
the data phase but is moved additionally by the number of clocks specified by
TDCeff (or SSP in the mcp2518fd case).

Here I do not follow you. The SSP, as specified in ISO 11898-1
is "specified by its distance from the start of the bit
time". Either you do not use TDC and the measurement is done on
the SP according to the tseg values, either you do use TDC and
the measurement is done on the SSP according to the TDC
values. There is no mention of mixing the tseg and tdc values.

P.S.: don't hesitate to invite your FPGA guy to this thread!


Yours sincerely,
Vincent