On Tue, 2025-02-18 at 11:11 +0000, Kevin Chen wrote:

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On Mon, 2025-02-17 at 13:00 +0100, Krzysztof Kozlowski wrote:

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On 17/02/2025 12:48, Kevin Chen wrote:

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+
+       pcc->mdev.parent = dev;
+       pcc->mdev.minor = MISC_DYNAMIC_MINOR;
+       pcc->mdev.name = devm_kasprintf(dev, GFP_KERNEL,
"%s%d",
DEVICE_NAME,

+                                       pcc->mdev_id);

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+       pcc->mdev.fops = &pcc_fops;
+       rc = misc_register(&pcc->mdev);
+       if (rc) {
+               dev_err(dev, "Couldn't register misc
device\n");
+               goto err_free_kfifo;
+       }

You cannot expose user-space interfaces from SoC drivers. Use
appropriate subsystem for this with proper ABI documentation.

See:
https://lore.kernel.org/all/bc5118f2-8982-46ff-bc75-d0c71475e909@a
pp.f
astmail.com/
and more discussions on LKML

Further, drivers/misc/aspeed-lpc-snoop.c already exists:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/c
ommit/?id=
9f4f9ae81d0affc182f54dd00285ddb90e0b3ae1

Kevin: Did you consider reworking it?

Andrew: No, I do not rework it but add the post code capture driver
using the SNOOP registers. As a result, I add some code in
aspeed_a2600_15 to check the SNOOP enable bit. PCC driver probe abort
if snoop is enabled.

Hmm, I think OpenBMC's history regarding POST code support caused some
confusion on my part. For whatever reason, the snoop device was used as a
source of POST codes despite the existence of the dedicated POST code
hardware since at least the AST2400, but...

What I know about the dedicated POST code hardware in ASPEED should be the same one in LPC module.

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PCC is used for port I/O byte snooping over eSPI.

... it seems that they're largely interchangeable, just with different hardware
features (PCC has DMA)? My impression is that the snoop device could also be
used over eSPI?

Yes, PCC has DMA to capture the POST code.
And snoop device also can be used over eSPI.

These two devices of PCC and snoop use the same port I/O of 80h and 81h.
But, in current usage of PCC, it can support a continuous, 4-bytes maximum region from port I/O 80h to 83h.
What I know about PCC or snoop usage, depends on INTEL platform or AMD platform.

For ASPEED, we want to upstream the PCC driver for the PCC usage.

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Nuvoton have a similar capability in their NPCM BMC SoC(s) with the
"BPC"
("BIOS POST Code" controller). There should be some consensus on the
binding and userspace interface.

This is still the case.

Andrew