Add the USB3 PHY node for the CIX Sky1 SoC and enable the PHY on the
Radxa Orion O6 board.
Signed-off-by: Hongliang Yang <redacted>
---
Changes in v6:
- Describe the PHY as a single provider with #phy-cells = <0> instead
of one child node per port.
---
arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 4 ++++
arch/arm64/boot/dts/cix/sky1.dtsi | 14 ++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
index e39c87774c12..5d57dd9ea299 100644
--- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
+++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
@@ -117,3 +117,7 @@ &s5_gpio2 {
&uart2 {
status = "okay";
};
+
+&usb3_phy4 {
+ status = "okay";
+};diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index 0a820f45feb9..c081b63a9848 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -606,6 +606,20 @@ mbox_ap2sfh: mailbox@80a0000 {
cix,mbox-dir = "tx";
};
+ usb3_phy4: usb-phy@9210000 {
+ compatible = "cix,sky1-usb3-phy";
+ reg = <0x00 0x09210000 0x00 0x40000>;
+ #phy-cells = <0>;
+ clocks = <&scmi_clk CLK_TREE_USB3A_PHY3_GATE>,
+ <&scmi_clk CLK_TREE_USB3A_PHY_x2_REF>;
+ clock-names = "apb", "ref";
+ resets = <&s5_syscon SKY1_USBPHY_SS_RST_N>,
+ <&s5_syscon SKY1_USBPHY_SS_PST_N>;
+ reset-names = "core", "apb";
+
+ status = "disabled";
+ };
+
pcie_x8_rc: pcie@a010000 {
compatible = "cix,sky1-pcie-host";
reg = <0x00 0x0a010000 0x00 0x10000>,--
2.54.0