RE: [PATCH v3 0/9] Add Aspeed AST2700 SDRAM EDAC support

Subject: Re: [PATCH v3 0/9] Add Aspeed AST2700 SDRAM EDAC support

On Wed, Sep 16, 2026 at 01:30:37PM +0800, Ryan Chen wrote:

quoted

Add ECC error reporting for the Aspeed AST2700 SoC to the existing
aspeed_edac driver.

The AST2700 memory controller keeps the same overall EDAC programming
model as the earlier Aspeed BMC SoCs, but uses a different register
layout, a split interrupt status/clear/mask scheme and DDR4/DDR5 memory.
Rather than fork the driver, the existing code is first tidied and
generalised, then the AST2700 is added as one more per-SoC variant.

Patches 2-5 are bug fixes and cleanups to the existing driver.

You always put the bug fixes first in a set. So it should be 1-4 bugfixes, rest new
features.

--

Thanks your review.

I'll reorder for v4:

  1  EDAC/aspeed: Set the DIMM grain
  2  EDAC/aspeed: Free the interrupt before the mem_ctl_info on remove
  3  EDAC/aspeed: Clean up whitespace and include ordering
  4  EDAC/aspeed: Free the mem_ctl_info unconditionally on remove
  5  dt-bindings: edac: aspeed: Add AST2700 SDRAM EDAC
  6  EDAC/aspeed: Replace regmap with direct register access
  7  EDAC/aspeed: Abstract SoC differences behind chip data
  8  EDAC/aspeed: Add AST2700 support
  9  MAINTAINERS: Add a reviewer for the Aspeed EDAC driver

1 and 2 carry the Fixes: tags, 3 and 4 are the cleanups, and 5 onwards
is the AST2700 work.

Ryan