On Tue, Sep 15, 2026 at 11:32 AM Michal Wilczynski
[off-list ref] wrote:
+static int starfive_hdmi_phy_probe(struct platform_device *pdev)
+{
+ ret = clk_set_rate(inno->phyclk, 297000000);
+ if (ret) {
+ dev_err(dev, "Failed to set default rate: %d\n", ret);
+ goto err_del_clk_provider;
+ }
Hi Michal,
Can we drop these 5 lines?
When my 4K monitor comes up in mode (3840x2160@30, 297 MHz) the screen
stays blank.
When the first real modeset requests a mode whose pixel clock is also 297 MHz,
clk_set_rate(hdmi_pclk, 297000000) then sees cur == want and does nothing.
So the pre-PLL is never actually programmed.
Without these 5 lines inno->pixclock stays 0,
so the first modeset's clk_set_rate() always runs .set_rate() for real.
Together with my forgotten fix from May we can have working 4K@30 on the VF2.
https://lore.kernel.org/all/20260528184145.384114-1-domibel@debian.org/ (local)
Best
-Dominique