[PATCH v2 13/14] arm64: dts: st: add ADC nodes on stm32mp251
From: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Date: 2026-09-23 15:41:08
Also in:
linux-devicetree, linux-iio, lkml
Subsystem:
arm/stm32 architecture, the rest · Maintainers:
Maxime Coquelin, Alexandre Torgue, Linus Torvalds
Add analog-to-digital converter support on STM32MP25 SoC. It has 3 ADCs, split into two blocks: - ADC1 and ADC2 are tightly coupled. - ADC3 is managed independently. Define internal voltage channels in the SOC dtsi file, exception made of vbat/4 channel (to avoid undesired load on it, in case no conversion is needed on this channel). Choice is let to board implementation (via DT) to define it. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> --- Changes in v2: - Adopt dedicated compatible for each child ADC, drop "st,adc-trigger-sel" - Drop fallback generic match (serve no purpose) --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 112 +++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 82a8a6f1f881..5834755194a1 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi@@ -1450,6 +1450,118 @@ uart8: serial@40380000 { status = "disabled"; }; + adc_12: adc@404e0000 { + compatible = "st,stm32mp25-adc-core"; + reg = <0x404e0000 0x400>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_ADC12>; + clock-names = "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&CLUSTER_PD>; + access-controllers = <&rifsc 58>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp25-adc1"; + reg = <0x0>; + interrupt-parent = <&adc_12>; + interrupts = <0>; + dmas = <&hpdma 81 0x20 0x12>; + dma-names = "rx"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; + status = "disabled"; + channel@14 { + reg = <14>; + label = "vrefint"; + }; + }; + + adc2: adc@100 { + compatible = "st,stm32mp25-adc2"; + reg = <0x100>; + interrupt-parent = <&adc_12>; + interrupts = <1>; + dmas = <&hpdma 82 0x20 0x12>; + dma-names = "rx"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; + status = "disabled"; + channel@14 { + reg = <14>; + label = "vrefint"; + }; + channel@15 { + reg = <15>; + label = "vddcore"; + }; + channel@17 { + reg = <17>; + label = "vddcpu"; + }; + channel@18 { + reg = <18>; + label = "vddgpu"; + }; + }; + }; + + adc_3: adc@404f0000 { + compatible = "st,stm32mp25-adc-core"; + reg = <0x404f0000 0x400>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_ADC3>; + clock-names = "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 59>; + power-domains = <&CLUSTER_PD>; + status = "disabled"; + + adc3: adc@0 { + compatible = "st,stm32mp25-adc3"; + reg = <0x0>; + interrupt-parent = <&adc_3>; + interrupts = <0>; + dmas = <&hpdma 83 0x20 0x12>; + dma-names = "rx"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; + status = "disabled"; + channel@14 { + reg = <14>; + label = "vrefint"; + }; + channel@15 { + reg = <15>; + label = "vddcore"; + }; + channel@17 { + reg = <17>; + label = "vddcpu"; + }; + channel@18 { + reg = <18>; + label = "vddgpu"; + }; + }; + }; + rng: rng@42020000 { compatible = "st,stm32mp25-rng"; reg = <0x42020000 0x400>;
--
2.43.0