[PATCH 1/5] arm64: dts: fsd: Fix indentation of CPU nodes
From: Krzysztof Kozlowski <hidden>
Date: 2026-09-09 14:18:16
Also in:
linux-devicetree, linux-samsung-soc, lkml
Subsystem:
arm/samsung s3c, s5p and exynos arm architectures, arm/tesla fsd soc support, the rest · Maintainers:
Krzysztof Kozlowski, Peter Griffin, Alim Akhtar, Linus Torvalds
Drop one tab too much to fix dt-check-style warning: fsd.dtsi:198: [indent-consistent] indent mismatch (expected depth 3 * '\t') Signed-off-by: Krzysztof Kozlowski <redacted> --- arch/arm64/boot/dts/tesla/fsd.dtsi | 310 ++++++++++++++++++------------------- 1 file changed, 155 insertions(+), 155 deletions(-)
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index 6766c78243a3..d076ea634f4e 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi@@ -96,196 +96,196 @@ core3 { /* Cluster 0 */ cpucl0_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x000>; - enable-method = "psci"; - clock-frequency = <2400000000>; - cpu-idle-states = <&cpu_sleep>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&cpucl_l2>; + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x000>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&cpu_sleep>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl0_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x001>; - enable-method = "psci"; - clock-frequency = <2400000000>; - cpu-idle-states = <&cpu_sleep>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&cpucl_l2>; + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x001>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&cpu_sleep>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl0_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x002>; - enable-method = "psci"; - clock-frequency = <2400000000>; - cpu-idle-states = <&cpu_sleep>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&cpucl_l2>; + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x002>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&cpu_sleep>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl0_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x003>; - enable-method = "psci"; - cpu-idle-states = <&cpu_sleep>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&cpucl_l2>; + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x003>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; /* Cluster 1 */ cpucl1_0: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x100>; - enable-method = "psci"; - clock-frequency = <2400000000>; - cpu-idle-states = <&cpu_sleep>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&cpucl_l2>; + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x100>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&cpu_sleep>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl1_1: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x101>; - enable-method = "psci"; - clock-frequency = <2400000000>; - cpu-idle-states = <&cpu_sleep>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&cpucl_l2>; + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x101>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&cpu_sleep>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl1_2: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x102>; - enable-method = "psci"; - clock-frequency = <2400000000>; - cpu-idle-states = <&cpu_sleep>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&cpucl_l2>; + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x102>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&cpu_sleep>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl1_3: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x103>; - enable-method = "psci"; - clock-frequency = <2400000000>; - cpu-idle-states = <&cpu_sleep>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&cpucl_l2>; + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x103>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&cpu_sleep>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; /* Cluster 2 */ cpucl2_0: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x200>; - enable-method = "psci"; - clock-frequency = <2400000000>; - cpu-idle-states = <&cpu_sleep>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&cpucl_l2>; + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x200>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&cpu_sleep>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl2_1: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x201>; - enable-method = "psci"; - clock-frequency = <2400000000>; - cpu-idle-states = <&cpu_sleep>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&cpucl_l2>; + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x201>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&cpu_sleep>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl2_2: cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x202>; - enable-method = "psci"; - clock-frequency = <2400000000>; - cpu-idle-states = <&cpu_sleep>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&cpucl_l2>; + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x202>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&cpu_sleep>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl2_3: cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x203>; - enable-method = "psci"; - clock-frequency = <2400000000>; - cpu-idle-states = <&cpu_sleep>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&cpucl_l2>; + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x203>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&cpu_sleep>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl_l2: l2-cache0 {
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2.53.0