[PATCH v6 15/27] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs
From: Louis-Alexis Eyraud <hidden>
Date: 2026-09-04 15:59:30
Also in:
linux-clk, linux-devicetree, linux-mediatek, lkml
Subsystem:
common clk framework, the rest · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Linus Torvalds
Add new set of PLL FHCTL clock operations, that uses the new prepare and unprepare methods, added in PLL for MT8189 SoC to support this logic. Reviewed-by: Brian Masney <redacted> Signed-off-by: Louis-Alexis Eyraud <redacted> --- drivers/clk/mediatek/clk-pllfh.c | 10 ++++++++++ drivers/clk/mediatek/clk-pllfh.h | 2 ++ 2 files changed, 12 insertions(+)
diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pllfh.c
index cc73eb4f87e6..f36dbc7fa06d 100644
--- a/drivers/clk/mediatek/clk-pllfh.c
+++ b/drivers/clk/mediatek/clk-pllfh.c@@ -47,6 +47,16 @@ static const struct clk_ops mtk_pllfh_ops = { .set_rate = mtk_fhctl_set_rate, }; +const struct clk_ops mtk_pllfh_setclr_ops = { + .is_prepared = mtk_pll_is_prepared, + .prepare = mtk_pll_prepare_setclr, + .unprepare = mtk_pll_unprepare_setclr, + .recalc_rate = mtk_pll_recalc_rate, + .determine_rate = mtk_pll_determine_rate, + .set_rate = mtk_fhctl_set_rate, +}; +EXPORT_SYMBOL_GPL(mtk_pllfh_setclr_ops); + static struct mtk_pllfh_data *get_pllfh_by_id(struct mtk_pllfh_data *pllfhs, int num_fhs, int pll_id) {
diff --git a/drivers/clk/mediatek/clk-pllfh.h b/drivers/clk/mediatek/clk-pllfh.h
index d32bfe194ec4..a9eb7558de1c 100644
--- a/drivers/clk/mediatek/clk-pllfh.h
+++ b/drivers/clk/mediatek/clk-pllfh.h@@ -69,6 +69,8 @@ struct fh_operation { int (*ssc_enable)(struct mtk_fh *fh, u32 rate); }; +extern const struct clk_ops mtk_pllfh_setclr_ops; + int mtk_clk_register_pllfhs(struct device *dev, const struct mtk_pll_data *plls, int num_plls, struct mtk_pllfh_data *pllfhs, int num_pllfhs,
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2.55.0