[PATCH v6 11/27] clk: mediatek: pll: Factorise pll power on/off sequences
From: Louis-Alexis Eyraud <hidden>
Date: 2026-09-04 15:59:30
Also in:
linux-clk, linux-devicetree, linux-mediatek, lkml
Subsystem:
common clk framework, the rest · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Linus Torvalds
In order to prepare the MT8189 SoC support, that requires different registers to control PLL status and perform reset BAR, and so a different sets of clock operations, split the pll power on and off sequences from mtk_pll_prepare/unprepare functions into private subfunctions. Reviewed-by: Brian Masney <redacted> Signed-off-by: Louis-Alexis Eyraud <redacted> --- drivers/clk/mediatek/clk-pll.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 4b0f7e2bfc5a..2aaf2871ecf6 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c@@ -223,9 +223,8 @@ int mtk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) return 0; } -int mtk_pll_prepare(struct clk_hw *hw) +static void mtk_pll_power_on(struct mtk_clk_pll *pll) { - struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); u32 r; r = readl(pll->pwr_addr) | CON0_PWR_ON;
@@ -235,6 +234,25 @@ int mtk_pll_prepare(struct clk_hw *hw) r = readl(pll->pwr_addr) & ~CON0_ISO_EN; writel(r, pll->pwr_addr); udelay(1); +} + +static void mtk_pll_power_off(struct mtk_clk_pll *pll) +{ + u32 r; + + r = readl(pll->pwr_addr) | CON0_ISO_EN; + writel(r, pll->pwr_addr); + + r = readl(pll->pwr_addr) & ~CON0_PWR_ON; + writel(r, pll->pwr_addr); +} + +int mtk_pll_prepare(struct clk_hw *hw) +{ + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); + u32 r; + + mtk_pll_power_on(pll); r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit); writel(r, pll->en_addr);
@@ -278,11 +296,7 @@ void mtk_pll_unprepare(struct clk_hw *hw) r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit); writel(r, pll->en_addr); - r = readl(pll->pwr_addr) | CON0_ISO_EN; - writel(r, pll->pwr_addr); - - r = readl(pll->pwr_addr) & ~CON0_PWR_ON; - writel(r, pll->pwr_addr); + mtk_pll_power_off(pll); } static int mtk_pll_prepare_fenc_setclr(struct clk_hw *hw)
--
2.55.0