On 27/08/2026 16:53, Marek Vasut wrote:
On 8/27/26 2:54 PM, Krzysztof Kozlowski wrote:
quoted
On 22/08/2026 09:46, Marek Vasut wrote:
quoted
+description:
+ USB2 PHY block in STM32 is attached to USB 2.0 Host controller and
+ USB 2.0 side of DWC3 DRD controller, and provides the USB LS/FS/HS
+ connectivity. Both PHYs are the FEMTO-PHY, but their configuration
+ bits in the system control register are different for each variant.
+
+maintainers:
+ - Fabrice Gasnier [off-list ref]
+ - Marek Vasut [off-list ref]
+ - Pankaj Dev [off-list ref]
+
+properties:
+ compatible:
+ enum:
+ - st,stm32mp25-usb2phy1
+ - st,stm32mp25-usb2phy2
+
+ "#clock-cells":
+ const: 1
+
As pointed out by different patchset built on top of it, this is wrong.
What is wrong in this (V3) of the patchset ? I think the ST patches were
fixing up V2 and what they were fixing up is already fixed here in V3.
Probably I got confused... but I had impression the ST patches were
adding here "reg" property, no?
Best regards,
Krzysztof