[PATCH 8/8] arm64: dts: st: Add USB nodes on stm32mp251
From: Marek Vasut <hidden>
Date: 2026-08-12 01:03:38
Also in:
linux-devicetree, linux-phy, linux-usb, lkml
Subsystem:
arm/stm32 architecture, the rest · Maintainers:
Maxime Coquelin, Alexandre Torgue, Linus Torvalds
From: Pankaj Dev <redacted> Add USB controller and PHY nodes to stm32mp251 DT. This includes two USB 2.0 FEMTO PHYs, USB 2.0 host controller and DWC3 DRD controller nodes. Signed-off-by: Marek Vasut <redacted> Signed-off-by: Pankaj Dev <redacted> --- Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Christian Bruel <christian.bruel@foss.st.com> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Neil Armstrong <neil.armstrong@linaro.org> Cc: Pankaj Dev <redacted> Cc: Rahul Kumar <redacted> Cc: Rob Herring <robh@kernel.org> Cc: Rosen Penev <redacted> Cc: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 61 ++++++++++++++++++++++++++ 1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 6e985f115b195..c54bd4554c33a 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi@@ -168,6 +168,26 @@ timer { arm,no-tick-in-suspend; }; + usb2_phy1: usb2-phy1 { + compatible = "st,stm32mp25-usb2phy1"; + #phy-cells = <0>; + #clock-cells = <0>; + st,syscfg = <&syscfg 0x2400>; + clocks = <&rcc CK_KER_USB2PHY1>; + resets = <&rcc USB2PHY1_R>; + status = "disabled"; + }; + + usb2_phy2: usb2-phy2 { + compatible = "st,stm32mp25-usb2phy2"; + #phy-cells = <0>; + #clock-cells = <0>; + st,syscfg = <&syscfg 0x2800>; + clocks = <&rcc CK_KER_USB2PHY2EN>; + resets = <&rcc USB2PHY2_R>; + status = "disabled"; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>;
@@ -1746,6 +1766,47 @@ stmmac_axi_config_1: stmmac-axi-config { }; }; + usbh_ohci: usb@482e0000 { + compatible = "generic-ohci"; + reg = <0x482e0000 0x1000>; + access-controllers = <&rifsc 63>; + clocks = <&usb2_phy1>, <&rcc CK_BUS_USB2OHCI>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy1>; + phy-names = "usb"; + resets = <&rcc USBH_R>; + status = "disabled"; + }; + + usbh_ehci: usb@482f0000 { + compatible = "generic-ehci"; + reg = <0x482f0000 0x1000>; + access-controllers = <&rifsc 63>; + clocks = <&usb2_phy1>, <&rcc CK_BUS_USB2EHCI>; + companion = <&usbh_ohci>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy1>; + phy-names = "usb"; + resets = <&rcc USBH_R>; + status = "disabled"; + }; + + usb3dr: usb@48300000 { + compatible = "st,stm32mp25-dwc3"; + reg = <0x48300000 0x100000>; + access-controllers = <&rifsc 66>; + clocks = <&rcc CK_KER_USB2PHY2>, + <&rcc CK_BUS_USB3DR>, + <&rcc CK_KER_USB2PHY2>; + clock-names = "ref", "bus_early", "suspend"; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy2>, <&combophy PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + resets = <&rcc USB3DR_R>; + st,syscfg = <&syscfg 0x4800>; + status = "disabled"; + }; + pcie_ep: pcie-ep@48400000 { compatible = "st,stm32mp25-pcie-ep"; reg = <0x48400000 0x100000>,
--
2.53.0