[PATCH RESEND 8/9] ARM: dts: stm32: add Ruiside ART-Pi2 board
From: Liu Changjie <hidden>
Date: 2026-07-26 16:14:23
Also in:
linux-devicetree, lkml
Subsystem:
arm/stm32 architecture, the rest · Maintainers:
Maxime Coquelin, Alexandre Torgue, Linus Torvalds
Add the STM32H7R7-based ART-Pi2 with 32 MiB of external HyperRAM, UART4 console pin configuration, user LEDs on PO1 and PO5, and the user button on PC13. Enable the four-bit microSD slot and reserve a coherent DMA pool for noMMU DMA allocations. Signed-off-by: Liu Changjie <redacted> --- arch/arm/boot/dts/st/Makefile | 1 + arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts | 100 +++++++++++++++++++ arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi | 63 ++++++++++++ 3 files changed, 164 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts create mode 100644 arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi
diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile
index 10c5d75f6..ae27a4ef9 100644
--- a/arch/arm/boot/dts/st/Makefile
+++ b/arch/arm/boot/dts/st/Makefile@@ -113,6 +113,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-disco.dtb \ stm32h747i-disco.dtb \ stm32h750i-art-pi.dtb \ + stm32h7r7l8-art-pi2.dtb \ stm32mp133c-prihmb.dtb \ stm32mp135f-dhcor-dhsbc.dtb \ stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtb \
diff --git a/arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts b/arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts
new file mode 100644
index 000000000..ead141817
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts@@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +/dts-v1/; + +#include "stm32h7r7.dtsi" +#include "stm32h7rs-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "RT-Thread ART-Pi2 STM32H7R7 board"; + compatible = "ruiside,art-pi2", "st,stm32h7r7"; + + chosen { + bootargs = "earlycon console=ttySTM0,115200"; + stdout-path = "serial0:115200n8"; + }; + + memory@90000000 { + device_type = "memory"; + reg = <0x90000000 0x02000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dma_pool: dma-pool { + compatible = "shared-dma-pool"; + no-map; + size = <0x00200000>; + linux,dma-default; + }; + }; + + aliases { + mmc0 = &sdmmc1; + serial0 = &uart4; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + + led_red: led-red { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpioo 1 GPIO_ACTIVE_HIGH>; + }; + + led_blue: led-blue { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpioo 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user { + label = "User"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart4 { + pinctrl-0 = <&uart4_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + max-frequency = <50000000>; + status = "okay"; +}; + +&clk_hse { + clock-frequency = <24000000>; +};
diff --git a/arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi
new file mode 100644
index 000000000..08f09f562
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi@@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2026 Liu Changjie <liucj1228@outlook.com> + */ + +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +&pinctrl { + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, AF11)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF11)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF11)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, AF11)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, AF11)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 8, AF11)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF11)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF11)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, AF11)>; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + + pins2 { + pinmux = <STM32_PINMUX('D', 2, AF11)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ + }; + }; + + uart4_pins_a: uart4-0 { + pins { + pinmux = <STM32_PINMUX('D', 0, AF8)>, /* UART4_RX */ + <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; +};
--
2.55.0