[PATCH v4 17/48] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address
From: Sascha Bischoff <hidden>
Date: 2026-07-24 10:53:56
Also in:
kvm, kvmarm
Subsystem:
kernel virtual machine for arm64 (kvm/arm64), the rest · Maintainers:
Marc Zyngier, Oliver Upton, Linus Torvalds
In order to properly emulate the operation of the IRS from KVM, we require storage for the MMIO register state. This change introduces struct vgic_v5_irs, and adds a pointer to it to the struct vgic_dist. This new data structure contains the storage for IRS MMIO state that is required for emulating the MMIO interface in KVM. This provides persistent storage, and a way to track data across MMIO writes, e.g., selecting an SPI and updating the configuration of it is two MMIO writes. Note that only a pointer to the data structure is added to struct vgic_dist as this new structure is very large, and hence it makes sense to dynamically allocate it and just provide a pointer to retrieve it in struct vgic_dist. In addition to adding a structure to store the MMIO state for the IRS, we add the base address in GPA space to struct vgic_v5_irs. Signed-off-by: Sascha Bischoff <redacted> --- include/kvm/arm_vgic.h | 86 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+)
diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
index faecde764fea3..25368c5cda5df 100644
--- a/include/kvm/arm_vgic.h
+++ b/include/kvm/arm_vgic.h@@ -409,6 +409,87 @@ struct vgic_v5_vm { bool vmte_allocated; }; +/*** GICv5 ***/ +struct vgic_v5_irs { + /* base addresses in guest physical address space: */ + gpa_t vgic_v5_irs_base; + + struct vgic_io_device iodev; + struct kvm_device *dev; + + /* IRS state - used for registers etc */ + struct { + u8 domain; + u8 pa_range; + bool virt; + bool setlpi; + bool mec; + bool mpam; + bool swe; + u16 irs_id; + } idr0; + + struct { + /* PE_CNT is populated from online_vcpus at runtime */ + u8 priority_bits; + } idr1; + + struct { + u8 id_bits; + u8 min_lpi_id_bits; + bool ist_levels; + u8 ist_l2sz; + bool istmd; + u8 istmd_sz; + } idr2; + + struct { + u32 spi_range; + } idr5; + + struct { + u32 spi_irs_range; + } idr6; + + struct { + u32 spi_base; + } idr7; + + struct { + u8 sh; + u8 oc; + u8 ic; + bool ist_ra; + bool ist_wa; + bool vmt_ra; + bool vpet_ra; + bool vmd_ra; + bool vmd_wa; + bool vped_ra; + bool vped_wa; + } cr1; + + struct { + u32 id; + } spi_selr; + + struct { + u32 iaffid; + } pe_selr; + + struct { + u8 lpi_id_bits; + u8 l2sz; + u8 istsz; + bool structure; + } ist_cfgr; + + struct { + bool valid; + u64 addr; + } ist_baser; +}; + struct vgic_dist { bool in_kernel; bool ready;
@@ -486,6 +567,11 @@ struct vgic_dist { * GICv5 per-VM data. */ struct vgic_v5_vm gicv5_vm; + + /* + * GICv5 IRS data. Dynamically allocated due to the size. + */ + struct vgic_v5_irs *vgic_v5_irs_data; }; struct vgic_v2_cpu_if {
--
2.34.1