Hi Frank,

On 2/10/26 18:11, Frank Li wrote:

The i.MX93 uses a newer version of the DW CSI-2 controller with a changed
register layout and an added IPI block.

What does this IPI block do? Please add a short description.

Why? The _write functions check for existance anyway, right?

+		dw_mipi_csi2rx_write(csi2, control, control);
+
+	ret = phy_power_on(csi2->phy);

Does it make sense to continue if phy_power_on fails? Check the return
value and return early.

Again, the dw_reg_exist checks seem superfluous.

All #defines at the top, as already pointed out before. Holds for all
other bit defines, too.

+
+static void imx93_csi2rx_dphy_assert_reset(struct dw_mipi_csi2rx_device *csi2)
+{
+	u32 val;
+
+	/* Release synopsis DPHY test codes from reset */
+	dw_mipi_csi2rx_write(csi2, dphy_rstz, 0);
+	dw_mipi_csi2rx_write(csi2, phy_shutdownz, 0);
+
+	val = dw_mipi_csi2rx_read(csi2, phy_tst_ctrl0);
+	val &= ~DPHY_TEST_CTRL0_TEST_CLR;
+	dw_mipi_csi2rx_write(csi2, phy_tst_ctrl0, val);
+
+	/*
+	 * ndelay is not necessary have MMIO operation, need dummy read to make
+	 * sure above write reach target.
+	 */
+	val = dw_mipi_csi2rx_read(csi2, phy_tst_ctrl0);
+	/* Wait for at least 15ns */
+	ndelay(15);
+	val |= DPHY_TEST_CTRL0_TEST_CLR;
+	dw_mipi_csi2rx_write(csi2, phy_tst_ctrl0, val);
+}
+
+#define CSI2RX_DPHY_STOPSTATE_CLK_LANE BIT(16)
+
+static void imx93_csi2rx_dphy_deassert_reset(struct dw_mipi_csi2rx_device *csi2)
+{
+	/* Release PHY from reset */
+	dw_mipi_csi2rx_write(csi2, phy_shutdownz, 0x1);
+	/*
+	 * ndelay is not necessary have MMIO operation, need dummy read to make
+	 * sure above write reach target.
+	 */
+	dw_mipi_csi2rx_read(csi2, phy_shutdownz);
+	ndelay(5);
+	dw_mipi_csi2rx_write(csi2, dphy_rstz, 0x1);
+
+	dw_mipi_csi2rx_read(csi2, dphy_rstz);
+	ndelay(5);
+}
+
+#define IPI_VCID_VC(x)			FIELD_PREP(GENMASK(1, 0), (x))
+#define IPI_VCID_VC_0_1(x)		FIELD_PREP(GENMASK(3, 2), (x))
+#define IPI_VCID_VC_2			BIT(4)
+
+#define IPI_DATA_TYPE_DT(x)		FIELD_PREP(GENMASK(5, 0), (x))
+#define IPI_DATA_TYPE_EMB_DATA_EN	BIT(8)
+
+#define IPI_MODE_CONTROLLER		BIT(1)
+#define IPI_MODE_COLOR_MODE16		BIT(8)
+#define IPI_MODE_CUT_THROUGH		BIT(16)
+#define IPI_MODE_ENABLE			BIT(24)
+
+#define IPI_MEM_FLUSH_AUTO		BIT(8)
+
+static void imx93_csi2rx_dphy_ipi_enable(struct dw_mipi_csi2rx_device *csi2)
+{
+	int dt = csi2->formats->csi_dt;
+	u32 val;
+
+	/* Do IPI soft reset */
+	dw_mipi_csi2rx_write(csi2, ipi_softrstn, 0x0);
+	dw_mipi_csi2rx_write(csi2, ipi_softrstn, 0x1);
+
+	/* Select virtual channel and data type to be processed by IPI */
+	val = IPI_DATA_TYPE_DT(dt);
+	dw_mipi_csi2rx_write(csi2, ipi_datatype, val);
+
+	/* Set virtual channel 0 as default */
+	val  = IPI_VCID_VC(0);
+	dw_mipi_csi2rx_write(csi2, ipi_vcid, val);
+
+	/*
+	 * Select IPI camera timing mode and allow the pixel stream
+	 * to be non-continuous when pixel interface FIFO is empty
+	 */
+	val = dw_mipi_csi2rx_read(csi2, ipi_mode);
+	val &= ~IPI_MODE_CONTROLLER;
+	val &= ~IPI_MODE_COLOR_MODE16;
+	val |= IPI_MODE_CUT_THROUGH;
+	dw_mipi_csi2rx_write(csi2, ipi_mode, val);
+
+	/* Memory is automatically flushed at each Frame Start */
+	val = IPI_MEM_FLUSH_AUTO;
+	dw_mipi_csi2rx_write(csi2, ipi_mem_flush, val);
+
+	/* Enable IPI */
+	val = dw_mipi_csi2rx_read(csi2, ipi_mode);
+	val |= IPI_MODE_ENABLE;
+	dw_mipi_csi2rx_write(csi2, ipi_mode, val);
+}
+
+static const struct dw_mipi_csi2rx_drvdata imx93_drvdata = {
+	.regs = &imx93_regs,
+	.dphy_assert_reset = imx93_csi2rx_dphy_assert_reset,
+	.dphy_deassert_reset = imx93_csi2rx_dphy_deassert_reset,
+	.ipi_enable = imx93_csi2rx_dphy_ipi_enable,
+};
+
 static const struct of_device_id dw_mipi_csi2rx_of_match[] = {
-	{
-		.compatible = "rockchip,rk3568-mipi-csi2", .data = &rk3568_drvdata,
-	},
+	{ .compatible = "fsl,imx93-mipi-csi2", .data = &imx93_drvdata, },

As pointed out before,
	{
		.compatible = "fsl,imx93-mipi-csi2",
		.data = &imx93_drvdata,
	},

Best regards,
Michael

+	{ .compatible = "rockchip,rk3568-mipi-csi2", .data = &rk3568_drvdata, },
 	{}
 };
 MODULE_DEVICE_TABLE(of, dw_mipi_csi2rx_of_match);