On 07/02/2026 12:27 am, Besar Wicaksono wrote:

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-----Original Message-----
From: James Clark <james.clark@linaro.org>
Sent: Monday, February 2, 2026 3:59 AM
To: Besar Wicaksono <redacted>; Ian Rogers
[off-list ref]
Cc: john.g.garry@oracle.com; will@kernel.org; mike.leach@linaro.org;
leo.yan@linux.dev; mark.rutland@arm.com;
alexander.shishkin@linux.intel.com; jolsa@kernel.org;
adrian.hunter@intel.com; peterz@infradead.org; mingo@redhat.com;
acme@kernel.org; namhyung@kernel.org; linux-tegra@vger.kernel.org; linux-
arm-kernel@lists.infradead.org; linux-perf-users@vger.kernel.org; linux-
kernel@vger.kernel.org; Thomas Makin [off-list ref]; Vikram Sethi
[off-list ref]; Rich Wiley [off-list ref]; Sean Kelley
[off-list ref]; Yifei Wan [off-list ref]; Thierry Reding
[off-list ref]; Jon Hunter [off-list ref]; Matt Ochs
[off-list ref]
Subject: Re: [PATCH] perf vendor events arm64: Add Tegra410 Olympus PMU
events

External email: Use caution opening links or attachments


On 30/01/2026 6:08 pm, Besar Wicaksono wrote:

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Thank you James and Ian for the comments.
I will try to address the spelling mistakes on v2.

Please see my other comments inline.

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-----Original Message-----
From: James Clark <james.clark@linaro.org>
Sent: Wednesday, January 28, 2026 3:37 AM
To: Ian Rogers <irogers@google.com>; Besar Wicaksono
[off-list ref]
Cc: john.g.garry@oracle.com; will@kernel.org; mike.leach@linaro.org;
leo.yan@linux.dev; mark.rutland@arm.com;
alexander.shishkin@linux.intel.com; jolsa@kernel.org;
adrian.hunter@intel.com; peterz@infradead.org; mingo@redhat.com;
acme@kernel.org; namhyung@kernel.org; linux-tegra@vger.kernel.org;

linux-

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arm-kernel@lists.infradead.org; linux-perf-users@vger.kernel.org; linux-
kernel@vger.kernel.org; Thomas Makin [off-list ref]; Vikram

Sethi

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[off-list ref]; Rich Wiley [off-list ref]; Sean Kelley
[off-list ref]; Yifei Wan [off-list ref]; Thierry Reding
[off-list ref]; Jon Hunter [off-list ref]; Matt Ochs
[off-list ref]
Subject: Re: [PATCH] perf vendor events arm64: Add Tegra410 Olympus

PMU

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events

External email: Use caution opening links or attachments


On 28/01/2026 8:03 am, Ian Rogers wrote:

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On Tue, Jan 27, 2026 at 3:00 PM Besar Wicaksono

[off-list ref] wrote:

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Add JSON files for NVIDIA Tegra410 Olympus core PMU events.
Also updated the common-and-microarch.json.

Signed-off-by: Besar Wicaksono <redacted>
---
    .../arch/arm64/common-and-microarch.json      |  90 +++
    tools/perf/pmu-events/arch/arm64/mapfile.csv  |   1 +
    .../arch/arm64/nvidia/t410/branch.json        |  45 ++
    .../arch/arm64/nvidia/t410/brbe.json          |   6 +
    .../arch/arm64/nvidia/t410/bus.json           |  48 ++
    .../arch/arm64/nvidia/t410/exception.json     |  62 ++
    .../arch/arm64/nvidia/t410/fp_operation.json  |  78 ++
    .../arch/arm64/nvidia/t410/general.json       |  15 +
    .../arch/arm64/nvidia/t410/l1d_cache.json     | 122 +++
    .../arch/arm64/nvidia/t410/l1i_cache.json     | 114 +++
    .../arch/arm64/nvidia/t410/l2d_cache.json     | 134 ++++
    .../arch/arm64/nvidia/t410/ll_cache.json      | 107 +++
    .../arch/arm64/nvidia/t410/memory.json        |  46 ++
    .../arch/arm64/nvidia/t410/metrics.json       | 722

++++++++++++++++++

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    .../arch/arm64/nvidia/t410/misc.json          | 646 ++++++++++++++++
    .../arch/arm64/nvidia/t410/retired.json       |  94 +++
    .../arch/arm64/nvidia/t410/spe.json           |  42 +
    .../arm64/nvidia/t410/spec_operation.json     | 230 ++++++
    .../arch/arm64/nvidia/t410/stall.json         | 145 ++++
    .../arch/arm64/nvidia/t410/tlb.json           | 158 ++++
    20 files changed, 2905 insertions(+)
    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/branch.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/brbe.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/bus.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/exception.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/fp_operation.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/general.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/l1d_cache.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/l1i_cache.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/l2d_cache.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/ll_cache.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/memory.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/metrics.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/misc.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/retired.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/spe.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/spec_operation.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/stall.json

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    create mode 100644 tools/perf/pmu-

events/arch/arm64/nvidia/t410/tlb.json

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diff --git a/tools/perf/pmu-events/arch/arm64/common-and-

microarch.json b/tools/perf/pmu-events/arch/arm64/common-and-
microarch.json

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index 468cb085d879..6af15776ff17 100644

--- a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json
+++ b/tools/perf/pmu-events/arch/arm64/common-and-

microarch.json

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@@ -179,6 +179,11 @@
            "EventName": "BUS_CYCLES",
            "BriefDescription": "Bus cycle"
        },
+    {
+        "EventCode": "0x001E",
+        "EventName": "CHAIN",
+        "BriefDescription": "Chain a pair of event counters."
+    },

Cool stuff :-)

For wider counters AMD does something similar, but should this be an
implementation detail rather than an exposed event? How does it
operate as an event?

CHAIN should be excluded from the json, it's used internally by the
driver when you want 64 bit counters. Userspace can't use it because it
can't control where counters are placed to make sure they're adjacent.

Sure, will address this in V2.

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[snip]

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diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv

b/tools/perf/pmu-events/arch/arm64/mapfile.csv

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index bb3fa8a33496..7f0eaa702048 100644

--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv

@@ -46,3 +46,4 @@
    0x00000000500f0000,v1,ampere/emag,core
    0x00000000c00fac30,v1,ampere/ampereone,core
    0x00000000c00fac40,v1,ampere/ampereonex,core
+0x000000004e0f0100,v1,nvidia/t410,core

diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/branch.json

b/tools/perf/pmu-events/arch/arm64/nvidia/t410/branch.json

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new file mode 100644
index 000000000000..532bc59dc573

--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/branch.json

@@ -0,0 +1,45 @@
+[
+    {
+        "ArchStdEvent": "BR_MIS_PRED",
+        "PublicDescription": "The Event counts Branches which are

speculatively executed and mis-predicted."

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nit: The capitalization on Event and Branches, as well as other words,
is a little unusual.

If there's nothing specific to this CPU then the public description
could be left out entierly. The common strings already say the same
thing as this:

       {
           "PublicDescription": "Mispredicted or not predicted branch
                                 speculatively executed",
           "EventCode": "0x10",
           "EventName": "BR_MIS_PRED",
           "BriefDescription": "Mispredicted or not predicted branch
                                speculatively executed"
       },

I will check on this and other events.

James, on a second thought, the description of the events was imported from
Olympus TRM. So just to keep my import flow simpler, if there is no major
concern, I would prefer to keep the description as is.

Thanks
Besar

Yes I think it's fine, you're already not overwriting BriefDescription 
so it will use the common ones from common-and-microarch.json by default 
unless running in verbose mode.