[PATCH v5] arm64: dts: ti: k3-am62l: support cpufreq scaling
From: Dhruva Gole <hidden>
Date: 2026-01-22 15:46:03
Also in:
linux-devicetree, linux-pm, lkml
Subsystem:
arm/texas instruments k3 architecture, the rest · Maintainers:
Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Linus Torvalds
Enable CPUFreq support for AM62L SoC by adding the relevant OPP efuse table syscon for speed grade detection. Add the operating-points-v2 table with CPU frequency steps from 200MHz to 1.25GHz. Specify the CPU clocks to reference the SCMI clock controller for frequency scaling. Signed-off-by: Dhruva Gole <redacted> --- Hello, This series adds CPU frequency scaling support for the TI AM62L3 SoC. The AM62L3 is a low-power, low-cost SoC from Texas Instruments. This series enables cpufreq support by: 1. Adding the SoC to the cpufreq-dt-platdev blocklist to prevent the generic driver from probing. 2. Extending the ti-cpufreq driver to support AM62L3 speed grading by reading the efuse. 3. Updating the device tree with the necessary operating points and clock configurations. Tested on AM62L3 EVM [1] [1] https://gist.github.com/DhruvaG2000/6dcceb80cf7bbd1e624ec210532538cb --- Changes in v5: - Update the opp-supported-hw value of 1Ghz entry to 0x02 - Minor reword of commit message - Link to v4: https://lore.kernel.org/all/20260122-am62l-dt-cpufreq-v1-1-fabcc15e25fa@ti.com/ (local) Changes in v4: - Sent as a stand alone patch. - Fix the bit fields in the OPPs as per Kendall's suggestion - Fix the scmi_clk ID of the second A53 core - Link to v3: https://lore.kernel.org/r/20260120-am62l-cpufreq-v3-0-8c69b80168a3@ti.com (local) Changes in v3: - Sorted the #defines and structs for am62l as well after am62a - Pick the R-by tag from Kendall - Link to v2: https://lore.kernel.org/r/20260116-am62l-cpufreq-v2-0-eac7e2e78d29@ti.com (local) Changes in v2: - Sort alphabetically while adding AM62L as per Krzysztof's comments - Link to v1: https://lore.kernel.org/r/20260116-am62l-cpufreq-v1-0-63d062317ae9@ti.com (local) --- arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-am62l3.dtsi | 47 +++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
index 61bfcdcfc66ea8d802a36ed43cd01fbbf3decc70..a42ccd0d2fcc4d204cae81508f839c44ce83f558 100644
--- a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi@@ -127,6 +127,11 @@ chipid: chipid@14 { bootph-all; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@2000 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x2000 0x8>;
diff --git a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
index da220b85151227c63f59b2b8ec48ae2ebb37e7bf..fc514e19f57d5318f851bad2756817dd7ec29b38 100644
--- a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi@@ -39,6 +39,8 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&scmi_clk 356>; }; cpu1: cpu@1 {
@@ -53,6 +55,8 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&scmi_clk 357>; }; };
@@ -64,4 +68,47 @@ l2_0: l2-cache0 { cache-line-size = <64>; cache-sets = <256>; }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0002>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0002>; + clock-latency-ns = <6000000>; + opp-suspend; + }; + }; };
--- base-commit: 9b7977f9e39b7768c70c2aa497f04e7569fd3e00 change-id: 20260116-am62l-cpufreq-1987a04a6f68 Best regards, -- Dhruva Gole [off-list ref]