[PATCH] arm64: dts: ti: k3-am62l: support cpufreq
From: Dhruva Gole <hidden>
Date: 2026-01-22 10:50:12
Also in:
linux-devicetree, lkml
Subsystem:
arm/texas instruments k3 architecture, the rest · Maintainers:
Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Linus Torvalds
Enable CPUFreq support for AM62L SoC by adding the relevant OPP efuse table syscon to k3-am62l-wakeup.dtsi for speed grade detection. Add the operating-points-v2 table with CPU frequency steps from 200MHz to 1.25GHz to k3-am62l3.dtsi Configure CPU clocks to reference the SCMI clock controller for frequency scaling This enables proper CPU frequency scaling capabilities for the AM62L SoC using the ARM SCMI protocol to interact with the power management firmware. Signed-off-by: Dhruva Gole <redacted> --- The driver changes were merged previously [0], and so the DT patch is now being posted seperately. Logs: root@am62lxx-evm:~# cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_available_frequencies 200000 400000 600000 800000 1000000 1250000 200000 400000 600000 800000 1000000 1250000 Changelog: - fix the bit fiels in the OPPs as per Kendall's suggestion - Fix the scmi_clk ID of the second A53 core [1] https://lore.kernel.org/all/20260120-am62l-cpufreq-v3-0-8c69b80168a3@ti.com/ (local) --- arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-am62l3.dtsi | 47 +++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
index 61bfcdcfc66ea8d802a36ed43cd01fbbf3decc70..a42ccd0d2fcc4d204cae81508f839c44ce83f558 100644
--- a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi@@ -127,6 +127,11 @@ chipid: chipid@14 { bootph-all; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@2000 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x2000 0x8>;
diff --git a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
index da220b85151227c63f59b2b8ec48ae2ebb37e7bf..26d3040ff53259daba21b39a55bb8a2ed65d4e8f 100644
--- a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi@@ -39,6 +39,8 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&scmi_clk 356>; }; cpu1: cpu@1 {
@@ -53,6 +55,8 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&scmi_clk 357>; }; };
@@ -64,4 +68,47 @@ l2_0: l2-cache0 { cache-line-size = <64>; cache-sets = <256>; }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0002>; + clock-latency-ns = <6000000>; + opp-suspend; + }; + }; };
--- base-commit: e3b32dcb9f23e3c3927ef3eec6a5842a988fb574 change-id: 20260122-am62l-dt-cpufreq-c24f0236ad15 Best regards, -- Dhruva Gole [off-list ref]