Re: [PATCH 3/3] arm64: dts: imx952-evk: add MT35XU01G spi nor flash
From: Han Xu <han.xu@nxp.com>
Date: 2026-01-14 16:43:53
Also in:
imx, linux-devicetree, linux-spi, lkml
On 26/01/14 02:49PM, Haibo Chen wrote:
Add spi nor flash MT35XU01G support, it support OCT DTR mode at 200MHz. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Han Xu <han.xu@nxp.com>
quoted hunk ↗ jump to hunk
--- arch/arm64/boot/dts/freescale/imx952-evk.dts | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+)diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 2c753fcbae3c5d545f5d835bd70492667061d626..534c93e527d0f3fb14ff3f21114993aae1d88a88 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts@@ -111,6 +111,25 @@ &usdhc2 { status = "okay"; }; +&xspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xspi1>; + status = "okay"; + + mt35xu01gbba: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xspi1_reset>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <200000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + &scmi_iomuxc { pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = <@@ -214,4 +233,26 @@ pinctrl_usdhc2_gpio: usdhc2gpiogrp { IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x31e >; }; + + pinctrl_xspi1: xspi1grp { + fsl,pins = < + IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x39e + IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x39e + IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x39e + IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x39e + IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x39e + IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x39e + IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x39e + IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x39e + IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI1_A_DQS 0x39e + IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x39e + IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x39e + >; + }; + + pinctrl_xspi1_reset: xspi1-reset-grp { + fsl,pins = < + IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x39e + >; + }; };-- 2.34.1