Hi Heiko,

Thanks for your review comment.

On Sat, 3 Jan 2026 at 16:09, Heiko Stübner [off-list ref] wrote:

Am Samstag, 3. Januar 2026, 06:25:04 Mitteleuropäische Normalzeit schrieb Anand Moon:

quoted

From: David Wu <redacted>

As per the RK3399 and RK3588 datasheets Rockchip I2C controllers feature
a SCL_OE_DB register (0x24). This register is used to configure the
debounce time for the SCL output enable signal, which helps prevent
glitches and ensures timing compliance during bus handover or slave clock
stretching.

Introduce a 'has_scl_oe_debounce' flag to rk3x_i2c_soc_data to
distinguish between hardware versions. For supported SoCs, calculate
the debounce counter dynamically based on the current clock rate
and program it during divider adaptation.

Signed-off-by: Anand Moon <redacted>
Signed-off-by: David Wu <redacted>

Signed-off-by lines are in the wrong order.

Original author first, then yours as you're the one handling
the patch last.

Ok, I will fix this in the next version, with a new feedback,

Also, does this fix a problem for you, or is this more a case of
"this looks useful"?

Actually, I am investigating a boot reset issue on the Radxa Rock 5B,
Specifically related to the fusb302 Type-C driver. So I was looking for
type-c fusb302 module to communicate with the I2C protocol.
I submitted small changes for this, waiting for feedback

Thanks
Heiko

Thanks
-Anand