Am Samstag, 3. Januar 2026, 06:25:04 Mitteleuropäische Normalzeit schrieb Anand Moon:

From: David Wu <redacted>

As per the RK3399 and RK3588 datasheets Rockchip I2C controllers feature
a SCL_OE_DB register (0x24). This register is used to configure the
debounce time for the SCL output enable signal, which helps prevent
glitches and ensures timing compliance during bus handover or slave clock
stretching.

Introduce a 'has_scl_oe_debounce' flag to rk3x_i2c_soc_data to
distinguish between hardware versions. For supported SoCs, calculate
the debounce counter dynamically based on the current clock rate
and program it during divider adaptation.

Signed-off-by: Anand Moon <redacted>
Signed-off-by: David Wu <redacted>

Signed-off-by lines are in the wrong order.

Original author first, then yours as you're the one handling
the patch last.


Also, does this fix a problem for you, or is this more a case of
"this looks useful"?

Thanks
Heiko